Graphene photodetector
A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.
1. A method of forming an electromagnetic radiation detector comprising:
forming at least one buried electrode in an insulator layer;
forming a graphene layer over said insulator layer;
forming at least one p-n junction within said graphene layer, wherein one of said at least one p-n junction does not overlie, and is laterally offset from a sidewall of, one of said at least one buried electrode;
forming at least one first upper electrode, wherein each of said at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of said at least one buried electrode;
forming at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, said at least one buried electrode; and
forming a measurement circuitry configured to measure an electrical current between, or an electrical voltage across, said at least one first upper electrode and said at least one second upper electrode.
2. The method of claim 1 , wherein said at least one buried electrode is formed by:
forming at least one trench in said insulator layer;
filling said at least one trench with at least one conductive material; and
removing portions of said at least one conductive material from above a plane of a top surface of said insulator layer, wherein remaining portions of said at least one conductive material constitute said at least one buried electrode.
3. The method of claim 1 , wherein said at least one first upper electrode and said at least one second upper electrode are simultaneously formed by a masked directional deposition of a conductive material.
4. The method of claim 1 , wherein each of said at least one buried electrode includes a pair of sidewalls that extends a long a lengthwise direction that is perpendicular to a spacing between one of said at least one first upper electrode and one of said at least one second upper electrode.
5. The method of claim 1 , wherein one of said at least one first upper electrode has a pair of parallel sidewalls separated by a first width and extending along a lengthwise direction, and one of said at least one second upper electrode has a pair of sidewalls separated by a second width and extending along said lengthwise direction.
6. The method of claim 5 , wherein a vertical plane including a sidewall of one of said at least one buried electrode exists between each neighboring pair of a first upper electrode and a second upper electrode.
7. The method of claim 1 , wherein said at least one first upper electrode is a plurality of first upper electrodes, said at least one second upper electrode is a plurality of second upper electrodes, and said plurality of first upper electrodes and said plurality of second upper electrodes are interlaced to provide an alternating arrangement of first and second upper electrodes along a horizontal direction.
8. The method of claim 1 , inducing charge carriers in regions of said grapheme layer that overlie said at least one buried electrode by applying an electrical bias to said at least one buried electrode, wherein said charge carriers have a conductivity type that is the opposite of a first conductivity type of said graphene layer as provided on said insulator layer prior to application of said electrical bias.
9. The method of claim 8 , wherein said application of said electrical bias is performed employing a bias circuitry configured to electrically bias said at least one buried electrode relative to said at least one first upper electrode or relative to said at least one second upper electrode.