Substrateless power device packages
A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
1. A power device package, comprising:
a substrate-less composite power semiconductor device that comprises:
a vertical conductive power semiconductor device chip, the device chip having a plurality of metal regions on a top surface, wherein the plurality of metal regions are electrically isolated by a passivation layer and wherein the device chip is characterized by a chip thickness;
solder bumps deposited on top of the metal regions; and
a wafer level molding surrounding the solder bumps and provided on top of the passivation layer, wherein the wafer level molding includes a polymer material and wherein the solder bumps extend above a top surface of the wafer level molding and wherein the wafer level molding has a thickness more than 3 times the chip thickness;
an external conductive interconnector connecting an electrode on the side of the device facing away from a leadframe to the leadframe; and
a molding compound that encapsulates the external conductive interconnector and the substrate-less composite power semiconductor device as a package.
2. The package of claim 1 wherein the external conductive interconnector is electrically connected to a top side of the substrate-less composite power semiconductor device through the solder bumps.
3. The package of claim 2 wherein the external conductive interconnector comprises a source clip.
4. The package of claim 1 wherein the substrate-less composite power semiconductor device is a flip chip device.
5. The package of claim 4 wherein the external conductive interconnector attached to a back side of the substrate-less composite power semiconductor device.
6. The package of claim 1 wherein the chip has a thickness less than or equal to about 25 microns.
7. The method of claim 1 , wherein the wafer level molding has a thickness that is greater than 150 microns.