Multi-core shared memory system with memory port to memory space mapping
A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.
1. A multi-core processor system comprising
a plurality of cores;
a memory controller including a plurality of ports corresponding to the cores; and
shared memory including physical address spaces assigned to each of the ports and memorizing correlation information which correlates a software performed with the cores and a number of a cores to which the software to be assigned, wherein
a first core among the cores assigns an execution core which performs software for execution among the cores based on the correlation information and each processing load of the cores;
the execution core sets a logical address space of the assigned software for execution, and the physical address space assigned to an execution port corresponding to the execution core to the memory controller, respectively; and
the first core makes the memory controller release connection with the ports corresponding to the cores except the execution core.
2. The multi-core processor system according to claim 1 , wherein the first core is configured to:
select, when a plurality of designated ports are present corresponding to the assigned cores, an arbitrary port from among the designated ports;
notify ports remaining after excluding the selected port from among the designated ports, of cancellation of connection of the ports remaining; and
aggregate physical address spaces accessible by the designated ports, wherein
the first core sets the aggregated physical address spaces in physical address spaces newly accessible by the selected port, and
the first core notifies the selected port of the newly accessible physical address spaces.
3. The multi-core processor system according to claim 2 , wherein the first core is configured to
detect, upon assigning a plurality of cores, a starting time for the assigned cores to simultaneously execute the software to be executed, wherein
the first core notifies the designated ports of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces,
the first core detects, as the starting time, the time at which the notification to the designated ports is completed, and
the first core notifies the software to be executed of the start of execution, after detecting the starting time.
4. The multi-core processor system according to claim 3 , wherein
the number of cores and the number of ports are equivalent.
5. A control method of a multi-core processor system comprising a plurality of cores; a memory controller including a plurality of ports corresponding to the cores; and shared memory including physical address spaces assigned to each of the ports and memorizing correlation information which correlates a software performed with the cores and a number of a cores to which the software to be assigned, the method being executed by the multi-core processor system and the method comprising:
assigning an execution core which performs software for execution among the cores based on the correlation information and each processing load of the cores;
setting a logical address space of the assigned software for execution, and the physical address space assigned to an execution port corresponding to the execution core to the memory controller; and
releasing connection of the memory controller with the ports corresponding to the cores except the execution core.
6. A non-transitory computer-readable recording medium storing a program causing a multi-core processor system comprising a plurality of cores; a memory controller including a plurality of ports corresponding to the cores; and shared memory including physical address spaces assigned to each of the ports and memorizing correlation information which correlates a software performed with the cores and a number of a cores to which the software to be assigned, to execute a process comprising:
assigning an execution core which performs software for execution among the cores based on the correlation information and each processing load of the cores;
setting a logical address space of the assigned software for execution, and the physical address space assigned to an execution port corresponding to the execution core to the memory controller; and
releasing connection of the memory controller with the ports corresponding to the cores except the execution core.