IP Library Granted Patent US 8,994,109
Granted Patent B2
US 8,994,109 · App. 13/832,373 · Granted Mar 31, 2015

High-K heterostructure

Inventors: Clement Merckling (Oullins, FR); Mario El-Kazzi (Lyons, FR); Guillaume Saint-Girons (Lyons, FR); Guy Hollinger (Moidieu-Detourbe, FR)
Assignees: STMicroelectronics SA; Centre National de la Recherche Scientifique; Ecole Centrale de Lyon
H01L29/045H01L29/513H01L21/02178H01L21/3147H01L21/02192H01L21/02299H01L21/02194H01L21/02293H01L21/02269H01L29/517H01L21/3162H01L21/28194H01L21/022
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Quick Facts
Patent No.
US 8,994,109
App. No.
13/832,373
Granted
Mar 31, 2015
Kind
B2
Abstract

A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al 2 O 3 Miller index (001) layer on a Si Miller index (001) substrate.

Claims (13)

1. A semiconductor device comprising a source, a gate, a drain, a well, and a dielectric layer between the well and the gate, wherein said well comprises a Si Miller index (001) substrate portion and the dielectric layer comprises a layer of 10 or less atomic monolayers of γ-Al 2 O 3 Miller index (001) material at least partly covered by a dielectric oxide layer.

2. A semiconductor device according to claim 1 , wherein said dielectric oxide layer is a high-k oxide material.

3. A semiconductor device according to claim 2 , wherein the high-k oxide material comprises crystalline Gd 2 O 3 Miller index (001) material.

4. A semiconductor device according to claim 2 , wherein the high-k oxide material is amorphous.

5. A multilayer substrate comprising a γ-Al 2 O 3 Miller index (001) layer on a Si Miller index (001) layer.

6. The substrate of claim 5 further comprising a dielectric oxide layer on top of the γ-Al 2 O 3 Miller index (001) layer.

7. The substrate of claim 6 wherein the dielectric oxide layer is a high-k oxide layer.

8. The substrate of claim 6 wherein the dielectric oxide layer is crystalline.

9. The substrate of claim 8 wherein the crystalline dielectric oxide layer comprises Gd 2 O 3 Miller index (001) material.

10. The substrate of claim 6 wherein the dielectric oxide layer is amorphous.

11. The substrate of claim 5 wherein the Si Miller index (001) layer supports at least one semiconductor device.

12. The substrate of claim 11 wherein the semiconductor device is a MOS transistor including a dielectric gate oxide layer on top of the γ-Al 2 O 3 Miller index (001) layer.

13. The substrate of claim 5 wherein the γ-Al 2 O 3 Miller index (001) layer is a layer of 10 or less atomic monolayers thickness.

Assignments (1)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
Priority Claims (1)
WO PCT/IB2007/003415 · Aug 28, 2007 · international
Continuity (2)
Division 12675733 · Apr 30, 2010
Related Publication 20130200440A1 · Aug 8, 2013