Granted Patent B2

US 8,996,788 · App. 13/370,114 · Granted Mar 31, 2015

Inventor: Amir Nassie (Haifa, IL)

Assignee: Densbits Technologies Ltd.

G06F12/0246G06F13/16G11C16/00G11C16/10

Abstract

Claims (86)

1. A method, for performing operations with a flash memory device, the method comprising:

receiving ,by a flash memory controller, a request to perform a requested operation with the flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation ; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the programmable module comprises a programmable signal generator;

wherein the method comprises:

determining whether to execute the requested operation by the programmable signal generator or by the multiple operation phase circuits;

wherein if it is determined to execute the requested operation by the programmable signal generator then executing the requested operation by the programmable signal generator;

wherein if it is determined to execute the requested operation by the multiple operation phase circuits then executing the requested operation by the plurality of operation phase circuits.

2. The method according to claim 1

wherein the multiple operation phase circuits comprise a command phase circuit, an address phase circuit and a program phase circuit.

3. The method according to claim 1 , wherein the multiple selected instructions are selected from a group of instructions that comprise a command instruction, an address instruction, a data read instruction, a data program instruction and at least one management instruction indicative of at least one of (a) a timing of an execution of another command, and (b) an order of execution of a plurality of commands.

4. The method according to claim 3 , wherein the at least one management instruction is a jump instruction.

5. The method according to claim 3 , wherein the group of instructions further comprises a release instruction for stopping a control of the flash memory device on the flash memory device.

6. The method according to claim 3 , wherein the group of instructions further comprises an interrupt instruction for interrupting a processor that is coupled to the flash memory device and to the flash memory controller.

7. The method according to claim 1 , wherein the determining is responsive to a capability of the plurality of operation phase circuits to generate a combination of waveforms mandated by the requested operation.

8. A method, for performing operations with a flash memory device, the method comprising:

receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the flash memory device is a first flash memory device and supports a first interface specification; wherein the flash memory controller is coupled to another flash memory device that supports another interface specification, wherein the other interface specification differs from the first interface specification; wherein the method comprises:

receiving another request to perform another requested operation with the other flash memory device;

selecting multiple selected instructions to be executed by the programmable module, based upon (a) the other interface specification and (b) the other requested operation; and

executing the multiple selected instructions by the programmable module.

9. A method, for performing operations with a flash memory device, the method comprising:

receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

powering up the flash memory controller; retrieving firmware from the flash memory device;

executing the firmware by an internal controller of the flash memory controller; wherein the executing of the firmware comprises determining the type of the flash memory device and retrieving at least a portion of a group of instructions, wherein the group of instructions comprises the selected instructions.

10. A non-transitory computer readable medium that stores instructions for:

receiving a request to perform a requested operation with a flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the programmable module comprises a programmable signal generator;

wherein the non-transitory computer readable medium stores instructions for:

determining whether to execute the requested operation by the programmable signal generator or by the multiple operation phase circuits;

wherein if it is determined to execute the requested operation by the programmable signal generator then executing the requested operation by the programmable signal generator;

wherein if it is determined to execute the requested operation by the multiple operation phase circuits then executing the requested operation by the plurality of operation phase circuits.

11. The non-transitory computer readable medium according to claim 10

wherein the multiple operation phase circuits comprise a command phase circuit, an address phase circuit and a program phase circuit.

12. The non-transitory computer readable medium according to claim 10 , wherein the selected instructions are selected from a group of instructions that comprise a command instruction, an address instruction, a data read instruction, a data program instruction and at least one management instruction indicative of at least one of (a) a timing of an execution of another command, and (b) an order of execution of a plurality of commands.

13. The non-transitory computer readable medium according to claim 12 , wherein the at least one management instruction is a jump instruction.

14. The non-transitory computer readable medium according to claim 12 , wherein the group of instructions further comprises a release instruction for stopping a control of the flash memory device on the flash memory device.

15. The non-transitory computer readable medium according to claim 12 , wherein the group of instructions further comprises an interrupt instruction for interrupting a processor that is coupled to the flash memory device and to the flash memory controller.

16. The non-transitory computer readable medium according to claim 10 that stores instructions for determining in response to a capability of the plurality of operation phase circuits to generate a combination of waveforms mandated by the requested operation.

17. A non-transitory computer readable medium that stores instructions for:

receiving a request to perform a requested operation with a flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the flash memory device is a first flash memory device and supports a first interface specification; wherein the flash memory controller is coupled to another flash memory device that supports another interface specification, wherein the other interface specification differs from the first interface specification; wherein the non-transitory computer readable medium stores instructions for:

receiving another request to perform another requested operation with the other flash memory device;

selecting multiple selected instructions to be executed by the programmable module, based upon (a) the other interface specification and (b) the other requested operation ; and

executing the multiple selected instructions by the programmable module.

18. A non-transitory computer readable medium that stores instructions for:

receiving a request to perform a requested operation with a flash memory device;

selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and

executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

powering up the flash memory controller; retrieving firmware from the flash memory device;

executing the firmware by an internal controller of the flash memory controller; wherein the executing of the firmware comprises determining the type of the flash memory device and retrieving at least a portion of a group of instructions, wherein the group of instructions comprises the selected instructions.

19. A flash memory controller, comprising:

an input port arranged to receive a request to perform a requested operation with a flash memory device;

a programmable module arranged to execute multiple selected instructions, wherein the multiple selected instructions are selected by the flash memory controller based upon (a) an interface specification supported by the flash memory device and (b) the requested operation;

wherein the programmable module comprises multiple operation phase circuits that are arranged to execute a plurality of the selected instructions; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the programmable module comprises a programmable signal generator;

wherein the flash memory controller is arranged to:

determine whether to execute the requested operation by the programmable signal generator or by the multiple operation phase circuits;

wherein if it is determined to execute the requested operation by the programmable signal generator then execute the requested operation by the programmable signal generator;

wherein if it is determined to execute the requested operation by the multiple operation phase circuits then execute the requested operation by the plurality of operation phase circuits.

20. The flash memory controller according to claim 19 , arranged to determine in response to a capability of the plurality of operation phase circuits to generate a combination of waveforms mandated by the requested operation.

21. The flash memory controller according to claim 19

wherein the multiple operation phase circuits comprise a command phase circuit, an address phase circuit and a program phase circuit.

22. The flash memory controller according to claim 19 , wherein the selected instructions are selected from a group of instructions that comprise a command instruction, an address instruction, a data read instruction, a data program instruction and at least one management instruction indicative of at least one of (a) a timing of an execution of another command, and (b) an order of execution of a plurality of commands.

23. The flash memory controller according to claim 22 , wherein the at least one management instruction is a jump instruction.

24. The flash memory controller according to claim 22 , wherein the group of instructions further comprises a release instruction for stopping a control of the flash memory device on the flash memory device.

25. The flash memory controller according to claim 22 , wherein the group of instructions further comprises an interrupt instruction for interrupting a processor that is coupled to the flash memory device and to the flash memory controller.

26. A flash memory controller, comprising:

an input port arranged to receive a request to perform a requested operation with a flash memory device;

a programmable module arranged to execute multiple selected instructions, wherein the multiple selected instructions are selected by the flash memory controller based upon (a) an interface specification supported by the flash memory device and (b) the requested operation;

wherein the programmable module comprises multiple operation phase circuits that are arranged to execute a plurality of the selected instructions; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the flash memory device is a first flash memory device and supports a first interface specification; wherein the flash memory controller is coupled to another flash memory device that supports another interface specification, wherein the other interface specification differs from the first interface specification; wherein the flash memory controller is arranged to receive another request to perform another requested operation with the other flash memory device; select multiple selected instructions to be executed by the programmable module, based upon (a) the other interface specification and (b) the other requested operation; and execute the multiple selected instructions by the programmable module.

27. A flash memory controller, comprising:

an input port arranged to receive a request to perform a requested operation with a flash memory device;

a programmable module arranged to execute multiple selected instructions, wherein the multiple selected instructions are selected by the flash memory controller based upon (a) an interface specification supported by the flash memory device and (b) the requested operation;

wherein the programmable module comprises multiple operation phase circuits that are arranged to execute a plurality of the selected instructions; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation;

wherein the flash memory controller is arranged to power up the flash memory controller; retrieving firmware from the flash memory device; execute the firmware by an internal controller of the flash memory controller; wherein the execution of the firmware comprises determining the type of the flash memory device and retrieving at least a portion of a group of instructions, wherein the group of instructions comprises the selected instructions.

Assignments (9)

Continuity (1)