System and method for providing stealth memory
The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.
1. A method performed on a computer system having a processing unit, a cache, and a memory device, the method comprising:
providing stealth memory to a first application, the stealth memory having an associated first physical address on the memory device;
identifying a cache line of the cache that is mapped to the first physical address associated with the stealth memory;
causing an alert when a second application attempts to access a second physical address to which the cache line is also mapped, wherein the second physical address is not associated with the stealth memory; and
responsive to the alert, performing a context switch away from the second application and loading the stealth memory into the cache such that the stealth memory is in the cache after another context switch back to the second application.
2. The method according to claim 1 , wherein the further comprising:
configuring a data structure to cause the alert.
3. The method according to claim 2 , wherein the alert comprises a page fault.
4. The method according to claim 1 , wherein the cache line comprises multiple slots and loading the stealth memory into the cache comprises accessing the first physical address such that, when the another context switch back to the second application occurs, the stealth memory is the most-recently used memory in the multiple slots of the cache line.
5. The method according to claim 1 , wherein the stealth memory comprises a virtual page that is at least partially stored in the cache line.
6. The method according to claim 5 , wherein providing the stealth memory comprises allocating a new page of virtual memory to the first application and the new page of virtual memory is stored in the memory device at the first physical address.
7. The method according to claim 5 , wherein providing the stealth memory comprises associating a previously-allocated page of virtual memory with the first physical address.
8. A computer system comprising:
a processing unit;
a cache having multiple cache lines; and
a memory device having computer-readable instructions which, when executed by the processing unit, cause the processing unit to:
provide stealth memory to a first application, the stealth memory having an associated first physical address on the memory device;
identify an individual cache line of the cache that is mapped to the first physical address associated with the stealth memory;
detect an attempt to access a second physical address to which the cache line is also mapped;
responsive to detection of the attempt to access the second physical address, perform a context switch to a memory monitor; and
via the memory monitor, load the stealth memory into the cache before the access to the second physical address occurs.
9. The computer system of claim 8 , wherein each of the cache lines has multiple slots.
10. The computer system of claim 8 , wherein the computer-readable instructions cause the processing unit to:
detect the attempt to access the second physical address via a page fault; and
determine that other page faults associated with other physical addresses to which the cache line is also mapped will not cause the stealth memory to be evicted from the cache.
11. The computer system of claim 8 , wherein the access is attempted by a second application.
12. The computer system of claim 11 , wherein the computer-readable instructions cause the processing unit to:
load the stealth memory into the cache by accessing the first physical address.
13. The computer system of claim 11 , wherein the computer-readable instructions cause the processing unit to:
maintain a first mapping between a first virtual address provided to the first application and the first physical address on the memory device; and
maintain a second mapping between a second virtual address provided to the second application and the second physical address on the memory device.
14. One or more computer-readable storage media comprising instructions which, when executed by one or more processing devices, cause the one or more processing devices to perform acts comprising:
providing stealth memory to a first application, the stealth memory having an associated first physical address on a memory device storing first data;
identifying a cache line of a cache that is mapped to the first physical address associated with the stealth memory;
detecting an attempt by a second application to access second data stored at a second physical address to which the cache line is also mapped, wherein the second physical address is not associated with the stealth memory; and
responsive to detecting the attempt by the second application to access the second data stored at the second physical address, perform a first context switch away from the second application, access the first physical address so that the stealth memory is loaded into the cache, and perform a second context back to the second application once the stealth memory is loaded into the cache.
15. The one or more computer-readable storage media of claim 14 , wherein the stealth memory comprises a first virtual page of memory associated with the first physical address and the second physical address is associated with a second virtual address of a second virtual page.
16. The one or more computer-readable storage media of claim 15 wherein the cache line has multiple slots, the acts further comprising:
tracking multiple page faults for the second virtual page and one or more other virtual pages having corresponding other physical addresses to which the cache line is also mapped; and
responsive to another attempt to access a further physical address to which the cache line is also mapped, designating the second virtual page as a victim page and evicting the second virtual page from the cache while at least some of the one or more other virtual pages remain in at least some of the multiple slots of the cache line with the stealth memory responsive to determining that the second virtual page is the least recently used virtual page.
17. The one or more computer-readable storage media of claim 16 , the acts further comprising:
tracking a number of allowable page faults before designating the second virtual page as the victim page, the number of allowable page faults being based on set associativity of the cache, wherein the cache implements a least-recently used cache replacement algorithm.
18. The one or more computer-readable storage media of claim 16 , the acts further comprising:
tracking a number of allowable page faults before designating the second virtual page as the victim page, the number of allowable page faults being based on a pseudo least-recently used cache replacement algorithm implemented by the cache.
19. The one or more computer-readable storage media of claim 16 , the acts further comprising:
designating the second virtual page as the victim page responsive to a determination that the second virtual page is least recently used relative to the one or more other virtual pages.
20. The one or more computer-readable storage media of claim 16 , embodied as a non-volatile storage device from which the instructions are read into the memory device.