N-way memory barrier operation coalescing

1. A computer-implemented method for processing memory barrier instructions, the method comprising:

receiving a first memory barrier instruction for a first thread group that includes multiple parallel execution threads;

blocking the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order;

receiving, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads;

coalescing the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction;

tagging each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands;

combining the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream;

transmitting the tagged memory command stream and memory transactions for the first thread group that are prior to the first memory barrier instruction in program order to a memory management unit to process the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order, the first set of memory transactions, the first memory barrier instruction, and the second memory barrier instruction;

determining that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory; and

releasing both the first memory barrier instruction to allow the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order to be executed and the second memory barrier instruction to allow the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order to be executed.

2. The method of claim 1 , further comprising, in response to receiving the first memory barrier instruction, outputting a memory barrier accept signal that includes the first coalescing index.

3. The method of claim 2 , further comprising:

receiving a third memory barrier instruction for a third thread group that includes multiple parallel execution threads;

blocking the execution of memory transactions for the third thread group that are subsequent to the third memory barrier instruction in program order;

receiving, subsequent to the third memory barrier instruction, a second set of memory transactions and a fourth memory barrier instruction for at least a fourth thread group that includes multiple execution threads;

coalescing the third memory barrier instruction and the fourth memory barrier instruction to generate a second coalesced memory barrier instruction;

tagging each transaction in the second set of memory transactions with a second coalescing index associated with the second coalesced memory barrier instruction to generate second tagged memory commands;

combining the second tagged memory commands and the second coalesced memory barrier instruction to generate a second taqqed memory command stream;

transmitting the second tagged memory command stream and memory transactions for the third thread group that are prior to the third memory barrier instruction in program order to the memory management unit to process the memory transactions for the third thread group that are prior to the third memory barrier instruction in program order, the second set of memory transactions, the third memory barrier instruction, and the fourth memory barrier instruction;

determining that the memory transactions for the third thread group that are prior to the third memory barrier instruction in program order and the second set of memory transactions are committed to memory; and

releasing both the third memory barrier instruction to allow the memory transactions for the third thread group that are subsequent to the third memory barrier instruction in program order to be executed and the fourth memory barrier instruction to allow the memory transactions for the fourth thread group that are subsequent to the fourth memory barrier instruction in program order to be executed.

4. The method of claim 3 , further comprising, in response to receiving the third memory barrier instruction, outputting a second memory barrier accept signal that includes the second coalescing index.

5. The method of claim 3 , wherein the second tagged memory command stream and memory transactions for the third thread group that are prior to the third memory barrier instruction in program order are transmitted to the memory management unit prior to determining that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory.

6. The method of claim 1 , wherein the step of determining comprises waiting for a memory barrier acknowledgement signal from the memory management unit that indicates that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory.

7. The method of claim 1 , further receiving an acknowledgement from the memory management unit once the coalesced memory barrier instruction has been processed prior to releasing the first memory barrier instruction and the second memory barrier instruction.

8. A computing system, comprising:

a memory; and

a parallel processing subsystem coupled to the memory and comprising:

an instruction scheduling unit configured to:

issue for execution a first memory barrier instruction for a first thread group that includes multiple parallel execution threads;

issue for execution, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads;

block the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order;

block the execution of memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order; and

release both the first memory barrier instruction to allow execution of the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order and the second memory barrier instruction to allow execution of the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order when an acknowledgement signal is received;

a memory management unit configured to process memory transactions and memory barrier instructions; and

a memory barrier instruction execution unit that is configured to:

receive the first memory barrier instruction;

receive the first set of memory transactions and the second memory barrier instruction;

coalesce the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction;

tag each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands; and

combine the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream.

9. The computing system of claim 8 , wherein the memory barrier instruction execution unit is further configured to:

transmit the tagged memory command stream and memory transactions for the first thread group that are prior to the first memory barrier instruction in program order to a memory management unit to process the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order, the first set of memory transactions, the first memory barrier instruction, and the second memory barrier instruction;

determine that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory; and

transmit the acknowledgement signal to the instruction scheduling unit.

10. The computing system of claim 8 , wherein the memory barrier instruction execution unit is further configured to, in response to receiving the first memory barrier instruction, output a memory barrier accept signal that includes the first coalescing index.

11. A processing subsystem comprising:

an instruction scheduling unit configured to:

issue for execution a first memory barrier instruction for a first thread group that includes multiple parallel execution threads;

issue for execution, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads;

block the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order;

block the execution of memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order; and

release both the first memory barrier instruction to allow execution of the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order and the second memory barrier instruction to allow execution of the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order when an acknowledgement signal is received;

a memory management unit configured to process memory transactions and memory barrier instructions; and

a memory barrier instruction execution unit that is configured to:

receive the first memory barrier instruction;

receive the first set of memory transactions and the second memory barrier instruction;

coalesce the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction

tag each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands; and

combine the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream.

12. The processing subsystem of claim 11 , wherein the memory barrier instruction execution unit is further configured to, in response to receiving the first memory barrier instruction, output a memory barrier accept signal that includes the first coalescing index.

13. The processing subsystem of claim 12 , wherein the memory barrier instruction execution unit is further configured to:

receive a third memory barrier instruction for a third thread group that includes multiple execution threads;

receive a second set of memory transactions and a second memory barrier instruction for a fourth thread group that includes multiple execution threads;

coalesce the third memory barrier instruction and the fourth second memory barrier instruction to generate a second coalesced memory barrier instruction;

tag each transaction in the second set of memory transactions with a second coalescing index associated with the second coalesced memory barrier instruction to generate second tagged memory commands; and

combine the second tagged memory commands and the second coalesced memory barrier instruction to generate a second tagged memory command stream.

14. The processing subsystem of claim 13 , wherein the memory barrier instruction execution unit is further configured to, in response to receiving the third memory barrier instruction, outputting a second memory barrier accept signal that includes the second coalescing index.

15. The processing subsystem of claim 13 , wherein the memory barrier instruction execution unit is further configured to transmit the second tagged memory command stream and memory transactions for the third thread group that are prior to the third memory barrier instruction in program order to the memory management unit prior to determining that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory.

16. The processing subsystem of claim 11 , wherein the memory barrier instruction execution unit is further configured to:

transmit the tagged memory command stream and memory transactions for the first thread group that are prior to the first memory barrier instruction in program order to a memory management unit to process the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order, the first set of memory transactions, the first memory barrier instruction, and the second memory barrier instruction;

determine that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory; and

transmit the acknowledgement signal to the instruction scheduling unit.

17. The processing subsystem of claim 11 , wherein the memory barrier instruction execution unit is further configured to wait for a memory barrier acknowledgement signal from the memory management unit that indicates that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory.

18. The processing subsystem of claim 17 , the memory barrier instruction execution unit is further configured to receive an acknowledgement from the memory management unit once the coalesced memory barrier instruction has been processed prior to releasing the first memory barrier instruction and the second memory barrier instruction.