Selective activation of programming schemes in analog memory cell arrays
A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.
1. An apparatus, comprising:
a plurality of memory cells; and
a control circuit configured to:
receive data for storage in the plurality of memory cells;
store a first portion of the received data using a first programming scheme that requires a first period of time to store the first portion of the received data;
select a second programming scheme responsive to an evaluation of a criterion, and
store a second portion of the received data using the second programming scheme, wherein the second programming scheme requires a second period of time to store the second portion of the received data;
wherein the first period of time is less than the second period of time.
2. The apparatus of claim 1 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the control circuit is further configured to determine a wear level for at least a portion of the plurality of memory cells.
3. The apparatus of claim 1 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the control circuit is further configured to determine a number of programming and erasure (P/E) cycles previously applied to at least a portion of the plurality of memory cells.
4. The apparatus of claim 1 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the control circuit is further configured to determine a number of read errors for at least a portion of the plurality of memory cells.
5. The apparatus of claim 1 , wherein the criterion is dependent upon a voltage level of a power supply signal coupled to the plurality of memory cells.
6. The apparatus of claim 1 , wherein the criterion is dependent upon a temperature of at least a portion of the plurality of memory cells.
7. A method, comprising:
receiving data to store in a memory unit, wherein the memory unit includes a plurality of memory cells;
storing a first portion of the data in the memory unit using a first programming scheme, wherein the first programming scheme requires a first period of time to store the first portion of the data;
selecting a second programming scheme responsive to an evaluation of a criterion, and
storing a second portion of the data in the memory unit using the second programming scheme, wherein the second programming scheme requires a second period of time to store the second portion of the data;
wherein the first period of time is less than the second period of time.
8. The method of claim 7 , wherein selecting the second programming scheme responsive to the evaluation of the criterion comprises determining a wear level for at least a portion of the plurality of memory cells.
9. The method of claim 7 , wherein selecting the second programming scheme responsive to the evaluation of the criterion comprises determining a number of programming and erasure (P/E) cycles previously applied to at least a portion of the plurality of memory cells.
10. The method of claim 7 , wherein selecting the second programming scheme responsive to the evaluation of the criterion comprises determining a number of read errors for at least a portion of the plurality of memory cells.
11. The method of claim 7 , wherein the criterion is dependent upon a level of interference affecting at least a portion of the plurality of memory cells.
12. The method of claim 7 , wherein the criterion is dependent upon a retention time of at least a portion of the plurality of memory cells.
13. The method of claim 7 , wherein the criterion is dependent upon a temperature of at least a portion of the plurality of memory cells.
14. A system, comprising:
a host processor; and
a memory unit coupled to the host processor, wherein the memory unit includes a plurality of memory cells, and wherein the memory unit is configured to:
receive data from the host processor;
store a first portion of the received data using a first programming scheme, wherein the first programming scheme requires a first period of time to store the first portion of the received data;
select a second programming scheme responsive to an evaluation of a criterion, and
store a second portion of the received data using the second programming scheme, wherein the second programming scheme requires a second period of time to store the second portion of the received data;
wherein the first period of time is less than the second period of time.
15. The system of claim 14 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the memory unit is further configured to determine a wear level for at least a portion of the plurality of memory cells.
16. The system of claim 14 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the memory unit is further configured to determine a number of programming and erasure (P/E) cycles previously applied to at least a portion of the plurality of memory cells.
17. The system of claim 14 , wherein to select the second programming scheme responsive to the evaluation of the criterion, the control circuit is further configured to determine a number of read errors for at least a portion of the plurality of memory cells.
18. The system of claim 14 , wherein the criterion is dependent upon a voltage level of a power supply signal coupled to the plurality of memory cells.
19. The system of claim 14 , wherein the criterion is dependent upon a temperature of at least a portion of the plurality of memory cells.
20. The system of claim 14 , wherein the criterion is dependent upon a level of interference affecting at least a portion of the plurality of memory cells.