System and method for selective error checking

1. An information handling system (IHS), comprising:

a memory system that includes a first memory portion that is configured to store error checking information and a second memory portion that is configured to store error checking information;

a memory controller system that is coupled to the memory system, wherein the memory controller system includes memory controller system memory segmentation information, and wherein the memory controller system is further configured to:

receive a write request that includes write data and that is directed to one of the first memory portion and second memory portion;

determine, in response to the write request being directed to the first memory portion that is configured to store error checking information, that the memory controller system memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generate error check data and provide the error check data along with the write data to the first memory portion; and

determine, in response to the write request being directed to the second memory portion that is configured to store error checking information, that the memory controller system memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, provide the write data to the second memory portion without generating error check data.

2. The IHS of claim 1 , wherein the first memory portion includes memory portion memory segmentation information, and wherein the first memory portion is configured to:

receive a read command for read data from the memory controller system; and

determine that the memory portion memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generate error check data and provide the error check data along with the read data to the memory controller system.

3. The IHS of claim 1 , wherein the second memory portion includes memory portion memory segmentation information, and wherein the second memory portion is configured to:

receive a read command for read data from the memory controller system; and

determine that the memory portion memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, provide the read data to the memory controller system without generating error check data.

4. The IHS of claim 1 , further comprising:

a memory segmentation system that is coupled to the memory controller system, the first memory portion, and the second memory portion, wherein the memory segmentation system is configured to determine system memory segmentation information by:

allocating the memory system into the first memory portion and the second memory portion, wherein the first memory portion and the second memory portion are designated by at least one of physical address ranges, virtual address ranges, and sets of operating system pages; and

designating that the first memory portion be subject to error checking and that the second memory portion be free of error checking; and

wherein the memory controller system memory segmentation information is at least a portion of the system memory segmentation information and the memory portion memory segmentation information is at least a portion of the system memory segmentation information, and wherein the memory segmentation system is configured to provide the memory controller system memory segmentation information to the memory controller system and provide the memory portion memory segmentation information to the first memory portion and the second memory portion.

5. The IHS of claim 4 , wherein the memory segmentation system includes an allocation system that is coupled to an initialization system, and wherein the allocation system is configured to perform the allocating of the memory system into the first memory portion and the second memory portion and the designating that the first memory portion be subject to error checking and that the second memory portion be free of error checking, and wherein the initialization system is configured to provide the memory controller system memory segmentation information to the memory controller system and provide the memory portion memory segmentation information to the first memory portion and the second memory portion.

6. The IHS of claim 4 , wherein the memory controller system memory segmentation information is associated with portions of the memory system that are controlled by the memory controller system and that include the first memory portion and the second memory portion.

7. The IHS of claim 4 , wherein the memory portion memory segmentation information is associated with portions of the memory system that are accessed simultaneously by the memory controller system and that include the first memory portion and the second memory portion.

8. The IHS of claim 4 , wherein the providing the memory portion memory segmentation information to the first memory portion and the second memory portion includes providing first memory portion memory segmentation information to the first memory portion, and providing second memory portion memory segmentation information to the second memory portion, and wherein the first memory portion memory segmentation information is associated with portions of the memory system that are accessed simultaneously by the memory controller system and that include the first memory portion but not the second memory portion, and wherein the second memory portion memory segmentation information is associated with portions of the memory system that are accessed simultaneously by the memory controller system and that include the second memory portion but not the first memory portion.

9. The IHS of claim 1 , wherein the memory controller system includes a plurality of memory controllers that each control a portion of the memory system.

10. The IHS of claim 1 , further comprising:

a plurality of subsystems coupled to the memory controller system, wherein the memory controller system memory segmentation information indicates that data associated with a first subsystem should be subject to error checking and that indicates that data associated with a second subsystem that supports error checking should be free of error checking.

11. A memory controller system, comprising:

a memory system connection;

at least one memory controller coupled to the memory system connection, wherein the at least one memory controller includes memory segmentation information, and wherein the at least one memory controller is configured to:

receive a write request that includes write data and that is directed to one of a first memory portion that is configured to store error checking information and a second memory portion that is configured to store error checking information, wherein the first memory portion and the second memory portion are each coupled to the memory system connection;

determine, in response to the write request being directed to the first memory portion that is configured to store error checking information, that the memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generate error check data and provide the error check data along with the write data to the first memory portion; and

determine, in response to the write request being directed to the second memory portion that is configured to store error checking information, that the memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, provide the write data to the second memory portion without generating error check data.

12. The system of claim 11 , wherein the at least one memory controller is configured to:

receive a read request for read data that is directed to one of the first memory portion and second memory portion that are each coupled to the memory system connection;

send a read command through the memory system connection according to the read request;

receive the read data along with error check data through the memory system connection in response to the read request being directed to the first memory portion and the memory segmentation information indicating that data associated with the first memory portion should be subject to error checking and, in response, process the error check data prior to providing the read data to a processing system; and

receive the read data without error check data through the memory system connection in response to the read request being directed to the second memory portion and the memory segmentation information indicating that data associated with the second memory portion should be free of error checking, in response, provide the read data to the processing system.

13. The system of claim 11 , further comprising:

a memory segmentation system connection coupled to the at least one memory controller, wherein the at least one memory controller is configured to receive the memory segmentation information from a memory segmentation system that is coupled to the memory segmentation system connection.

14. The system of claim 11 , wherein the memory segmentation information is associated with portions of a memory system that are coupled to the memory system connection, controlled by the at least one memory controller, and that include the first memory portion and the second memory portion.

15. The system of claim 11 , further comprising:

at least one subsystem connection coupled to the at least one memory controller, wherein the memory segmentation information indicates that data associated with a first subsystem that is coupled to the at least one subsystem connection should be subject to error checking and that indicates that data associated with a second subsystem that is coupled to the at least one subsystem connection and that supports error checking should be free of error checking.

16. A method for error checking a memory subsystem, comprising:

storing, by at least one memory controller, memory controller memory segmentation information;

receiving, by the at least one memory controller, a write request that includes write data and that is directed to one of a first memory portion that is configured to store error checking information and a second memory portion that is configured to store error checking information;

determining, by the at least one memory controller in response to the write request being directed to the first memory portion that is configured to store error checking information, that the memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generating error check data and providing the error check data along with the write data to the first memory portion; and

determining, by the at least one memory controller in response to the write request being directed to the second memory portion that is configured to store error checking information, that the memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, providing the write data to the second memory portion without generating error check data.

17. The method of claim 16 , further comprising:

storing, by the first memory portion, memory portion memory segmentation information;

receiving, by the first memory portion, a read command for read data from the memory controller; and

determining, by the first memory portion, that the memory portion memory segmentation information indicates that data associated with the first memory portion should be subject to error checking and, in response, generating error check data and providing the error check data along with the read data to the memory controller.

18. The method of claim 16 , further comprising:

storing, by the second memory portion, memory portion memory segmentation information;

receiving, by the second memory portion, a read command for read data from the memory controller; and

determining, by the second memory portion, that the memory portion memory segmentation information indicates that data associated with the second memory portion should be free of error checking and, in response, providing the read data to the memory controller without generating error check data.

19. The method of claim 16 , further comprising:

determining, by a memory segmentation system, system memory segmentation information by:

allocating, by the memory segmentation system, a memory system into the first memory portion and the second memory portion; and

designating, by the memory segmentation system, that the first memory portion be subject to error checking and that the second memory portion be free of error checking;

wherein the memory controller memory segmentation information is at least a portion of the system memory segmentation information and the memory portion memory segmentation information is at least a portion of the system memory segmentation information, and wherein the memory segmentation system provides the memory controller memory segmentation information to the memory controller and provide the memory portion memory segmentation information to the first memory portion and the second memory portion.

20. The method of claim 19 , wherein the memory controller memory segmentation information is associated with portions of the memory system that are controlled by the memory controller and that include the first memory portion and the second memory portion, and wherein the memory portion memory segmentation information is associated with portions of the memory system that are accessed simultaneously by the memory controller and that include the first memory portion and the second memory portion.