Device and method for performing timing analysis
A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.
1. A device for performing timing analysis used in a programmable logic array system comprising:
a plurality of first basic I/O circuits to receive a plurality of under-test signals from an under-test unit;
a plurality of second basic I/O circuits;
a channel multiplexer to receive the under-test signals from the first basic I/O circuits to select at least a group of the under-test signals to be outputted to the second basic I/O circuits;
a plurality of high-speed I/O circuits having a logic level analyzing speed higher than that of the first and second basic I/O circuit, wherein the high-speed I/O circuits are connected to the second basic I/O circuits;
a sampling module to receive the group of under-test signals outputted from the second basic I/O circuits through the high-speed I/O circuits and to sample the group of under-test signals to generate a sample result; and
a timing analysis module to perform a timing analysis and measurement according to the sample result.
2. The device of claim 1 , wherein the logic level analyzing speed of the first basic I/O circuits and the second basic I/O circuits is at most 200 MHz.
3. The device of claim 1 , wherein the logic level analyzing speed of the high-speed I/O circuits is at least 1 GHz.
4. The device of claim 1 , further comprising a calibration module to store a timing calibration table such that the timing analysis module performs the timing analysis and measurement after the timing analysis module performs a timing calibration on the sample result of under-test signals according to the timing calibration table.
5. The device of claim 4 , wherein the timing calibration table records a path latency difference between any two of the first basic I/O circuits and the channel multiplexer and between any two of the second basic I/O circuits and the channel multiplexer.
6. The device of claim 1 , further comprising:
a plurality of first timing calibration modules each connected between one of the first basic I/O circuits and the channel multiplexer; and
a plurality of second timing calibration modules each connected between one of the second basic I/O circuits and the channel multiplexer, in which the first timing calibration modules and the second timing calibration modules perform a timing calibration on the under-test signals according to a timing calibration information.
7. The device of claim 6 , wherein the timing calibration information is a path latency difference between any two of the first basic I/O circuits and the channel multiplexer and between any two of the second basic I/O circuits and the channel multiplexer.
8. The device of claim 6 , wherein each of the first timing calibration modules and the second timing calibration modules is a delay element.
9. The device of claim 1 , wherein the sampling module is a high speed serial to low speed parallel sampling module.
10. A method for performing timing analysis used in a device for performing timing analysis in a programmable logic array system, wherein the method comprises:
receiving a plurality of under-test signals from an under-test unit to a plurality of first basic I/O circuits;
receiving the under-test signals from the first basic I/O circuits to a channel multiplexer to select at least a group of the under-test signals to be outputted to a plurality of second basic I/O circuits;
receiving the group of under-test signals outputted from the second basic I/O circuits through a plurality of high-speed I/O circuits to sample the group of under-test signals to generate a sample result, wherein the high-speed I/O circuits have a logic level analyzing speed higher than that of the first and second basic I/O circuits; and
performing a timing analysis and measurement according to the sample result.
11. The method of claim 10 , further comprising performing the timing analysis and measurement after performing a timing calibration on the sample result of under-test signals according to a timing calibration table.
12. The method of claim 11 , wherein the timing calibration table records a path latency difference between any two of the first basic I/O circuits and the channel multiplexer and between any two of the second basic I/O circuits and the channel multiplexer.
13. The method of claim 10 , further comprising performing a timing calibration on the under-test signals according to a timing calibration information by a plurality of first timing calibration modules each connected between one of the first basic I/O circuits and the channel multiplexer and by a plurality of second timing calibration modules each connected between one of the second basic I/O circuits and the channel multiplexer.
14. The method of claim 13 , wherein the timing calibration information is a path latency difference between any two of the first basic I/O circuits and the channel multiplexer and between any two of the second basic I/O circuits and the channel multiplexer.