Dielectric charge trapping memory cells with redundancy
A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
1. A method of operating memory cells within an array of dielectric charge trapping memory cells, the array of dielectric charge trapping memory cells including a plurality of bit lines BL(i), for i between 0 and N, and a plurality of word lines WL(j), for j between 1 and M, the array including a plurality of columns of memory cells and a plurality of rows of memory cells, each column being disposed between bit line BL(i) and bit line BL(i+1), and each row R(j) of the memory cells being coupled to a corresponding word line WL(j), and wherein a memory cell in the array has a first charge trapping site adjacent to the bit line BL(i+1) and a second charge trapping site adjacent to the BL(i), comprising:
writing a data value in a logical cell for a selected column address A C (y), wherein y is between 1 and N−1, and a selected row address A R (x), wherein x is between 1 and M in the array, by applying program and erase operations to set threshold states representing said data value both in the first charge trapping site in the memory cell between bit lines BL(y−1) and BL(y), and in the second charge trapping site in the memory cell between bit lines BL(y) and BL(y+1); and
reading a data value for a selected column address A C (y), wherein y is between 1 and N−1, and a selected row address A R (x), wherein x is between 1 and M, by sensing the threshold states both in the first charge trapping site in the memory cell between bit lines BL(y−1) and BL(y), and in the second charge trapping site in the memory cell in column between bit lines BL(y) and BL(y+1), and determining that the data value is that corresponding with the highest sensed threshold state.
2. The method of claim 1 , wherein the program and erase operations store one bit per selected column address and selected row address, said determining includes using said highest threshold state as a logical value of “1,” using a lower threshold state as a logical value of “0,” and applying a logical OR operation to the assigned logical values.
3. The method of claim 1 , wherein the program operation applies a first program voltage to the word line WL(j) and a second program voltage to the bit line BL(i) causing charge to tunnel into the first charge trapping site in the memory cell between bit lines BL(i−1) and BL(i), and in the second charge trapping site in the memory cell between bit lines BL(i) and BL(i+1).
4. The method of claim 3 , wherein the program bias setting thresholds cause charge to tunnel from the word line.
5. The method of claim 4 , wherein the charge tunneling occurs through Fowler-Nordheim tunneling.
6. The method of claim 1 , wherein writing the data value further includes writing data values for multiple selected column addresses A C (y) and selected row addresses A R (x) in parallel.
7. An integrated circuit, comprising:
an array of dielectric charge trapping memory cells, the array of dielectric charge trapping memory cells including a plurality of bit lines BL(i), for i between 0 and N, and a plurality of word lines WL(j), for j between 1 and M, the array including a plurality of columns of memory cells and a plurality of rows of memory cells, each column being disposed between bit line BL(i) and bit line BL(i+1), and each row R(j) of the memory cells being coupled to a corresponding word line WL(j), and wherein a memory cell in the array has a first charge trapping site adjacent to the bit line BL(i+1) and a second charge trapping site adjacent to the BL(i); and
read and write circuitry coupled to the array configured to:
write a data value in a logical cell for a selected column address A C (y), wherein y is between 1 and N−1, and a selected row address A R (x), wherein x is between 1 and M in the array, by applying program and erase operations to set threshold states representing said data value both in the first charge trapping site in the memory cell between bit lines BL(y−1) and BL(y), and in the second charge trapping site in the memory cell between bit lines BL(y) and BL(y+1); and
read a data value for a selected column address A C (y), wherein y is between 1 and N−1, and a selected row address A R (x), wherein x is between 1 and M, by sensing the threshold states both in the first charge trapping site in the memory cell between bit lines BL(y−1) and BL(y), and in the second charge trapping site in the memory cell in column between bit lines BL(y) and BL(y+1), and determine that the data value is that corresponding with the highest sensed threshold state.
8. The integrated circuit of claim 7 , wherein the program and erase operations store one bit per selected column address and selected row address, said determining includes using said highest threshold state as a logical value of “1,” using a lower threshold state as a logical value of “0,” and applying a logical OR operation or a logical NOR operation to the assigned logical values.
9. The integrated circuit of claim 7 , wherein the program operation applies a first program voltage to the word line WL(j) and a second program voltage to the bit line BL(i) causing charge to tunnel into the first charge trapping site in the memory cell between bit lines BL(i−1) and BL(i), and in the second charge trapping site in the memory cell in column between bit lines BL(i) and BL(i+1).
10. The integrated circuit of claim 9 , wherein the program bias setting thresholds cause charge to tunnel from the word line.
11. The integrated circuit of claim 10 , wherein the charge tunneling occurs through Fowler-Nordheim tunneling.
12. The integrated circuit of claim 7 , including circuitry to write data values for multiple selected column addresses A C (y) and selected row addresses A R (x) in parallel.
13. The integrated circuit of claim 7 , wherein the array comprises multiple layers of memory cells.
14. The integrated circuit of claim 7 , wherein the array comprises thin film transistor memory cells.