Statistical circuit simulation

1. A computer implemented method for statistical circuit simulation, comprising:

providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit;

partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, wherein partitioning further comprises forming the groups of netlists according to proximity of variations of statistical parameters of the circuit, and wherein proximity of variations of statistical parameters comprises variations of threshold voltage of a transistor in a sub-threshold region, variations of threshold voltage of the transistor in a linear region, and variations of threshold voltage of the transistor in a saturation region;

simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, wherein the plurality of processors include a plurality of graphics processing units and a plurality of central processing units; and

storing the plurality of output data files in a memory.

2. The computer implemented method of claim 1 , wherein descriptions of the circuit further includes circuit netlists, and model library.

3. The computer implemented method of claim 1 , wherein partitioning comprises:

forming the groups of netlists to be simulated in a single instruction multiple data environment.

4. The computer implemented method of claim 1 , further comprises:

identifying a representative parameter to represent a group of statistical parameters, wherein the group of statistical parameters has substantially the same value as the representative parameter and the group of statistical parameters is substantially invariant.

5. The computer implemented method of claim 1 , wherein simulating the groups of netlists using a plurality of processors in parallel comprises:

maintaining the groups of netlists and their corresponding statistical parameters in a shared memory;

performing model evaluations using the plurality of graphics processing units; and

performing matrix solving, checking simulation convergence, and predicting next time step using the plurality of central processing units.

6. The computer implemented method of claim 5 , wherein the shared memory comprises:

a model evaluation queue configured to store one or more tasks to be processed by the plurality of graphics processing units; and

a task queue configured to store one or more tasks to be processed by the plurality of central processing units.

7. The computer implemented method of claim 6 further comprising:

performing load balancing by assigning one or more tasks from the model evaluation queue to be handled by the plurality of central processing units.

8. The computer implemented method of claim 6 further comprising:

performing load balancing by assigning one or more tasks from the task queue to be handled by the plurality of graphics processing units.

9. A system for performing statistical circuit simulation, comprising:

a plurality of processors and a shared memory configured to be used by the plurality of processors;

a simulator module configured to work with the plurality of processors, wherein the simulator module comprises

logic configured to provide descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit;

logic configured to partition the circuit into groups of netlists according to variations of statistical parameters of the circuit, wherein logic configured to partition the circuit further comprises logic configured to form the groups of netlists according to proximity of variations of statistical parameters of the circuit, and wherein proximity of variations of statistical parameters comprises variations of threshold voltage of a transistor in a sub-threshold region, variations of threshold voltage of the transistor in a linear region, and variations of threshold voltage of the transistor in a saturation region;

logic configured to simulate the groups of netlists using the plurality of processors in parallel to generate a plurality of output data files, wherein the plurality of processors include a plurality of graphics processing units and a plurality of central processing units; and

a memory for storing the plurality of output data files.

10. The system of claim 9 , wherein descriptions of the circuit further includes circuit netlist, and model library.

11. The system of claim 9 , wherein logic configured to partition the circuit comprises:

logic configured to form the groups of netlists to be simulated in a single instruction multiple data environment.

12. The system of claim 9 further comprises:

logic configured to identify a representative parameter to represent a group of statistical parameters, wherein the group of statistical parameters has substantially the same value as the representative parameter and the group of statistical parameters is substantially invariant.

13. The system of claim 9 , wherein logic configured to simulate the groups of netlists using a plurality of processors in parallel comprises:

logic configured to maintain the groups of netlists and their corresponding statistical parameters in a shared memory;

logic configured to perform model evaluations using the plurality of graphics processing units; and

logic configured to perform matrix solving, checking simulation convergence, and predicting next time step using the plurality of central processing units.

14. The system of claim 13 , wherein the shared memory comprises:

a model evaluation queue configured to store one or more tasks to be processed by the plurality of graphics processing units; and

a task queue configured to store one or more tasks to be processed by the plurality of central processing units.

15. The system of claim 14 further comprising:

logic configured to perform load balancing by assigning one or more tasks from the model evaluation queue to be handled by the plurality of central processing units.

16. The system of claim 14 further comprising:

logic configured to perform load balancing by assigning one or more tasks from the task queue to be handled by the plurality of graphics processing units.

17. A computer program product for statistical circuit simulation, comprising a non-transitory medium storing computer programs for execution by one or more computer systems, the computer program product comprising:

code for providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit;

code for partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, wherein code for partitioning further comprises code for forming the groups of netlists according to proximity of variations of statistical parameters of the circuit, and wherein proximity of variations of statistical parameters comprises variations of threshold voltage of a transistor in a sub-threshold region, variations of threshold voltage of the transistor in a linear region, and variations of threshold voltage of the transistor in a saturation region;

code for simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, wherein the plurality of processors include a plurality of graphics processing units and a plurality of central processing units; and

code for storing the plurality of output data files in a memory.