IP Library Granted Patent US 9,035,273
Granted Patent B2
US 9,035,273 · App. 13/323,927 · Granted May 19, 2015

Resistive switching memory device

Inventor: Sakyo Hirose (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01L29/8615H01L27/101H01L29/24H01L29/47H01L45/085H01L45/1226H01L45/147
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Quick Facts
Patent No.
US 9,035,273
App. No.
13/323,927
Granted
May 19, 2015
Kind
B2
Abstract

A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes.

Claims (17)

1. A resistive switching memory device comprising:

an oxide semiconductor selected from the group consisting of (Ba 1-x Sr x )Ti 1-y A y O 3 , Ti 1-z M z O 2 , and (R,Ca)MnO 3 , wherein A is at least one of Mn, Fe, and Co; 0 ≦x≦1.0 and 0.005≦y≦0.05, M is at least one of Fe, Co, Ni, and Cu; and 0.005≦z≦0.05, and R is any of La, Nd, Pr, Sm, Gd, Dy, Ho, and Y;

at least a first electrode, a second electrode, and a third electrode, each of the first, second and third electrodes being adjacent the oxide semiconductor; and

a power supply for control connected between the first electrode and the second electrode, wherein

the first electrode comprises a first material that forms a first Schottky barrier, the first Schottky barrier having a rectifying property and resistance change characteristics in a first interface region between the first electrode and the oxide semiconductor,

the second electrode comprises a second material that forms a second Schottky barrier, the second Schottky barrier having a rectifying property and resistance change characteristics in a second interface region between the second electrode and the oxide semiconductor,

the third electrode comprises a third material which forms a contact that is ohmic as compared to that of the first interface region and as compared to that of the second interface region, and

the power supply is configured to control a resistance of the first interface region.

2. The resistive switching memory device according to claim 1 , wherein each of the first, second and third electrodes are in contact with the oxide semiconductor.

3. The resistive switching memory device according to claim 1 , further comprising an insulating layer between the second electrode and the oxide semiconductor.

4. The resistive switching memory device according to claim 1 , wherein the oxide semiconductor is an n-type semiconductor.

5. The resistive switching memory device according to claim 1 , wherein the resistive switching memory device has a capacitor structure.

6. The resistive switching memory device according to claim 1 , wherein the first and second electrodes are adjacent a first surface of the oxide semiconductor, and the third electrode is adjacent a second surface of the oxide semiconductor, the first surface and the second surface of the oxide semiconductor being opposed to each other.

7. The resistive switching memory device according to claim 6 , further comprising an insulating substrate adjacent the third electrode.

8. The resistive switching memory device according to claim 1 , wherein the first, second and third electrodes are adjacent a first surface of the oxide semiconductor.

9. The resistive switching memory device according to claim 8 , further comprising an insulating substrate adjacent a second surface of the oxide semiconductor, the first surface and the second surface of the oxide semiconductor being opposed to each other.

10. The resistive switching memory device according to claim 1 , wherein the oxide semiconductor is a p-type semiconductor.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED ON REEL 027387 FRAME 0364. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 6, 2012
From: HIROSE, SAKYO
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 027817/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2011
From: HIROSE, SAKYO
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 027387/0364 →
Priority Claims (1)
JP 2009-142193 · Jun 15, 2009 · national
Continuity (2)
Continuation PCTJP2010060019 · Jun 14, 2010
Related Publication 20120132883A1 · May 31, 2012