System-wide power management control via clock distribution network

1. An apparatus for automatically controlling power dissipation in a parallel computing system that includes a plurality of processors, the apparatus comprising:

a computing device issuing a command signal, which represents a command, to the parallel computing system;

a clock pulse-width modulator receiving the command signal and a system clock signal, encoding the command, represented in the command signal, into the system clock signal to be distributed to the plurality of processors, the encoding including:

performing a logical OR operation between the command signal and the system clock signal and outputting a modified clock signal, the modified clock signal having one or more modified pulses wherein a modified pulse in the modified clock signal has a rising edge aligned with a rising edge of a corresponding pulse of the system clock signal but a width of the modified pulse being different from the corresponding pulse width of the system clock signal, the one or more modified pulses representing the command; and

the plurality of processors in the parallel computing system receiving the modified clock signal including the encoded command and adjusting power dissipation at one or more of the plurality of processors according to the encoded command.

2. The apparatus according to claim 1 , wherein the one or more of the plurality of processors synchronously respond to the encoded command.

3. The apparatus according to claim 1 , wherein the clock pulse-width modulator encodes the command in the system clock signal by using a pulse width modulation.

4. The apparatus according to claim 1 , where the command includes a periodic global synchronization signal for synchronizing the one or more of the plurality of processors.

5. The apparatus according to claim 1 , wherein the command initiates a power management action of the parallel computing system.

6. The apparatus according to claim 1 , wherein in response to the encoded command, the one or more of the plurality of processors adjust power dissipation by using one or more of: clock gating, dynamic frequency scaling (DFS), dynamic voltage scaling (DVS), and performance adjustment.

7. The apparatus according to claim 1 , wherein the computing device issues the command in response to data from sensors internal to the parallel computing system.

8. The apparatus according to claim 1 , wherein the computing device issues the command in response to data from sensors external to the parallel computing system.

9. The apparatus according to claim 1 , wherein the computing device issues the command in response to data center policies.

10. The apparatus according to claim 1 , wherein the computing device issues the command in response to time varying cost of electricity and cooling of the parallel computing system.

11. The apparatus according to claim 1 , wherein each partition of the parallel computing system reacts differently in response to the encoded command.

12. A method for automatically controlling power dissipation in a parallel computing system that includes a plurality of processors, the method comprising:

issuing, at a computing device, a command signal, which represents a command, to the parallel computing system;

receiving, at a clock pulse-width modulator, the command signal and a system clock signal;

encoding, at the clock pulse-width modulator, the command, represented in the command signal, into the system clock signal to be distributed to the plurality of processors, the encoding including:

performing a logical OR operation between the command signal and the system clock signal and outputting a modified clock signal, the modified clock signal having one or more modified pulses wherein a modified pulse in the modified clock signal has a rising edge aligned with a rising edge of a corresponding pulse of the system clock signal but a width of the modified pulse being different from the corresponding pulse width of the system clock signal, the one or more modified pulses representing the command; and

receiving, at the plurality of processors in the parallel computing system, the modified clock signal including the encoded command and adjusting, at one or more of the plurality of processors, power dissipation according to the encoded command.

13. The method according to claim 12 , wherein the one or more of the plurality of processors synchronously respond to the encoded command.

14. The method according to claim 12 , wherein the encoding the command in the system clock signal includes:

using a pulse width modulation.

15. The method according to claim 12 , where the command includes a periodic global synchronization signal for synchronizing the one or more of the plurality of processors.

16. The method according to claim 12 , wherein the command initiates a power management action of the parallel computing system.

17. The method according to claim 12 , wherein in response to the encoded command, the one or more of the plurality of processors adjust power dissipation by using one or more of: clock gating, dynamic frequency scaling (DFS), dynamic voltage scaling (DVS), and performance adjustment.

18. The method according to claim 12 , wherein the computing device issues the command in response to data from sensors internal to the parallel computing system.

19. The method according to claim 12 , wherein the computing device issues the command in response to data from sensors external to the parallel computing system.

20. The method according to claim 12 , wherein the computing device issues the command in response to data center policies.

21. The method according to claim 12 , wherein the computing device issues the command in response to time varying cost of electricity and cooling of the parallel computing system.

22. The method according to claim 12 , wherein each partition of the parallel computing system reacts differently in response to the encoded command.

23. A computer program product for automatically controlling power dissipation in a parallel computing system that includes a plurality of processors, the computer program product comprising a storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing a method, the method comprising:

issuing, at a computing device, a command signal, which represents a command, to the parallel computing system;

receiving, at a clock pulse-width modulator, the command signal and a system clock signal;

encoding, at the clock pulse-width modulator, the command, represented in the command signal, into the system clock signal to be distributed to the plurality of processors, the encoding including:

performing a logical OR operation between the command signal and the system clock signal and outputting a modified clock signal, the modified clock signal having one or more modified pulses wherein a modified pulse in the modified clock signal has a rising edge aligned with a rising edge of a corresponding pulses of the system clock signal but a width of the modified pulse being different from the corresponding pulse width of the system clock signal, the one or more modified pulses representing the command; and

receiving, at the plurality of processors in the parallel computing system, the modified clock signal including the encoded command and adjusting, at one or more of the plurality of processors, power dissipation according to the encoded command.

24. The computer program product according to claim 23 , wherein the one or more of the plurality of processors synchronously respond to the encoded command.

25. The computer program product according to claim 23 , wherein the clock pulse-width modulator encodes the command in the system clock signal by using a pulse width modulation.

26. The apparatus according to claim 1 , wherein the clock pulse-width modulator divides a frequency of the system clock signal.

27. The method according to claim 12 , further comprising:

dividing, by the clock pulse-width modulator, a frequency of the system clock signal.