IP Library Granted Patent US 9,041,149
Granted Patent B2
US 9,041,149 · App. 13/059,277 · Granted May 26, 2015

Gringo heterojunction bipolar transistor with a metal extrinsic base region

Inventors: Guillaume Boccardi (Lueven, BE); Mark C. J. C. M. Kramer (Sittard, NL); Johannes J. T. M. Donkers (Valkenswaard, NL); Li Jen Choi (Mountain View, CA); Stefaan Decoutere (Haasrode, BE); Arturo Sibaja-Hernandez (Heverlee, BE); Stefaan Van Huylenbroeck (Kessel-Lo, BE); Rafael Venegas (Heverlee, BE)
Assignee: NXP, B.V.
H01L29/1004H01L21/8249H01L27/0623H01L29/66242H01L29/66287
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Quick Facts
Patent No.
US 9,041,149
App. No.
13/059,277
Granted
May 26, 2015
Kind
B2
Abstract

The invention relates to a semiconductor device ( 30 ) comprising a substrate ( 1 ), a semiconductor body ( 25 ) comprising a bipolar transistor that comprises a collector region ( 3 ), a base region ( 4 ), and an emitter region ( 15 ), wherein at least a portion of the collector region ( 3 ) is surrounded by a first isolation region ( 2, 8 ), the semiconductor body ( 25 ) further comprises an extrinsic base region ( 35 ) arranged in contacting manner to the base region ( 4 ). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.

Claims (25)

1. A method of manufacturing a bipolar transistor comprising the steps:

a) forming a collector region on a substrate and forming an intrinsic base region on top of the collector region,

b) forming a first isolation region surrounding at least a portion of the collector region, and

c) forming an extrinsic base region including a metal layer, the extrinsic base region arranged adjacent to the intrinsic base region and in direct contact with the intrinsic base region,

wherein the step of forming the extrinsic base region including the metal layer includes:

forming a sacrificial layer arranged inside the extrinsic base region and at the top surface of the extrinsic base region,

depositing a pre-metal dielectric layer on top of the sacrificial layer of the extrinsic base region,

dry etching contact holes and/or contact stripes through the pre-metal dielectric layer to the top surface of the sacrificial layer, and

removing the sacrificial layer and replacing the removed sacrificial layer of the extrinsic base region by a metal layer.

2. The method of manufacturing a bipolar transistor according to claim 1 , further comprising before dry etching contact holes and/or contact stripes, planarizing the pre-metal dielectric layer by applying chemical mechanical planarization.

3. The method of manufacturing a bipolar transistor according to claim 2 , wherein the step of replacing the removed sacrificial layer of the extrinsic base region by a metal layer further includes: depositing a metal on top of the extrinsic base region for filling the contact holes and/or contact stripes.

4. The method of manufacturing a bipolar transistor according to claim 1 , before the step of depositing a pre-metal dielectric layer on top of the sacrificial layer: forming silicide spacers arranged inside the extrinsic base region and adjacent to the metal layer, where the silicide spacers are disposed between the metal layer and the intrinsic base region.

5. The method of manufacturing a bipolar transistor according to claim 2 , before the step of depositing a pre-metal dielectric layer on top of the sacrificial layer: providing SINGEN spacers arranged adjacent to the extrinsic base region by applying LPCVD followed by an anisotropic etch.

6. The method of manufacturing a bipolar transistor according to claim 1 , wherein the sacrificial layer includes poly-SiGe.

7. The method of manufacturing a bipolar transistor according to claim 1 , wherein the sacrificial layer includes an undoped poly-Si layer.

8. The method of manufacturing a bipolar transistor according to claim 1 , wherein the sacrificial layer includes an undoped poly-Si layer formed on top of a silicon dioxide layer.

9. The method of manufacturing a bipolar transistor according to claim 1 , wherein the extrinsic base region includes a doped Si layer, where the sacrificial layer is formed on top of the doped Si layer.

10. The method of manufacturing a bipolar transistor according to claim 9 , wherein a part of the doped Si layer of the extrinsic base region is formed to separate the sacrificial layer from the intrinsic base region, wherein the doped Si layer prevents the intrinsic base from being laterally etched during the sacrificial layer removal.

11. The method of manufacturing a bipolar transistor according to claim 2 , wherein the step of removing the sacrificial layer includes: removing the sacrificial layer by etching through the contact holes and/or contact stripes, the removal of the sacrificial layer forming a cavity in the extrinsic base region.

12. The method of manufacturing a bipolar transistor according to claim 11 , wherein the step of replacing the sacrificial layer includes: filling the cavity with a metal via the contact holes and/or contact stripes and forming the metal layer in the extrinsic base region.

13. The method of manufacturing a bipolar transistor according to claim 1 , wherein the metal layer is in direct contact with the intrinsic base region.

14. The method of manufacturing a bipolar transistor according to claim 1 , wherein the metal layer is in contact with the intrinsic base region via a silicide spacer.

15. The method of manufacturing a bipolar transistor according to claim 1 , wherein the metal layer is in contact with the intrinsic base region via a doped poly-Si layer.

16. The method of manufacturing a bipolar transistor according to claim 9 , wherein the extrinsic base region is separated from the emitter region by an oxide layer.

17. The method of manufacturing a bipolar transistor according to claim 3 , wherein the deposited metal is tungsten and the metal layer is a tungsten layer.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2011
From: BOCCARDI, GUILLAUME; KRAMER, MARK C. J. C. M.; DONKERS, JOHANNES J. T. M.; CHOI, LI JEN; DECOUTERE, STEFAAN; SIBAJA-HERNANDEZ, ARTURO; VAN HUYLENBROECK, STEFAAN; VENEGAS, RAFAEL
To: NXP B.V.; INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
Reel/Frame 026219/0028 →
Priority Claims (2)
EP 08162603 · Aug 19, 2008 · regional
EP 08166641 · Oct 15, 2008 · regional
Continuity (1)
Related Publication 20110198671A1 · Aug 18, 2011