Universal network interface controller
A universal network interface controller (UNIC) is provided for interfacing a host computer to a switch fabric, a packet network, or both. The UNIC includes ingress transmit logic designed to transmit switch fabric data in memory associated with the host computer to a switch fabric. The UNIC further includes egress receive logic designed to receive switch fabric data from the switch fabric to store the received switch fabric data in the host memory associated with the host computer. As an option, the ingress transmit logic may be further designed to transmit packet network data in memory associated with the host computer to a packet network, such as Ethernet, and the egress receive logic may be further designed to receive the packet network data from the packet network and to store the received switch fabric data and the received packet network data in the host memory associated with the host computer.
1. A network interface controller (NIC) for a host computer, comprising:
a bus interface communicatively coupled to a memory within the host computer; and
circuitry configured to:
receive a fabric packet and a network packet from the memory via the bus interface to be transmitted to at least one external device;
slice the fabric packet into at least one fabric cell; and
queue and schedule the at least one fabric cell and the network packet for transmission of the at least one fabric cell and the network packet over a switch fabric and a packet network, respectively, to the at least one external device,
wherein the circuitry comprises:
an ingress packet processor configured to define at least one virtual output queue (VOQ) in the memory and map at least one destination endpoint to the at least one VOQ; and
an ingress traffic manager configured to queue and de-queue the at least one fabric cell and the network packet in the at least one VOQ,
wherein the circuitry is:
configured to receive at least one egress fabric cell from the switch fabric and an egress network packet from the packet network and map the at least one egress fabric cell and the egress network packet to at least one egress queue, and
configured to manage the at least one egress queue.
2. The NIC of claim 1 , further comprising:
a fabric interface configured to communicate the at least one fabric cell over the switch fabric; and
a packet interface configured to communicate the network packet over the packet network.
3. The NIC of claim 1 , wherein the circuitry is further configured to determine whether to queue and schedule one or more of the at least one fabric cell and the network packet for unicast or multicast communication over the switch fabric and the packet network, respectively.
4. The NIC of claim 1 , wherein the circuitry is further configured to queue and schedule one or more of the at least one fabric cell and the network packet for communication over the switch fabric and the packet network, respectively, based on availability of the switch fabric and the packet network.
5. The NIC of claim 1 , wherein the circuitry is further configured to produce a switch fabric link and a packet network link based upon respective headers of the fabric packet and the network packet, the switch fabric link defining a first path through the switch fabric to a fabric destination endpoint, and the packet network link defining a second path through the packet network to a network destination endpoint.
6. The NIC of claim 1 , wherein the circuitry is configured to receive data from the switch fabric and the packet network, respectively, and store the data in the memory.
7. The NIC of claim 6 , wherein the circuitry is communicatively coupled to an input/output (I/O) interface associated with the host computer by direct memory access.
8. A network interface controller (NIC) for a host computer, comprising:
a bus interface communicatively coupled to a memory associated with the host computer; and
circuitry configured to receive a fabric packet and a network packet from the memory via the bus interface, slice the fabric packet into at least one fabric cell, and queue and schedule the at least one fabric cell and the network packet for communication over at least one of a switch fabric and a packet network,
wherein the circuitry comprises:
an ingress packet processor communicatively coupled to the host computer via the bus interface and configured to define at least one virtual output queue (VOQ) in the memory and map at least one destination endpoint to the at least one VOQ;
an ingress traffic manager communicatively coupled to the ingress packet processor and configured to queue and de-queue the at least one fabric cell and the network packet in the at least one VOQ; and
an ingress transmit processor communicatively coupled to the ingress traffic manager and configured to communicate the at least one fabric cell and the network packet over the switch fabric and the packet network, respectively, to at least one external device,
wherein the circuitry is:
configured to receive at least one egress fabric cell from the switch fabric and an egress network packet from the packet network and map the at least one egress fabric cell and the egress network packet to at least one egress queue, and
configured to manage the at least one egress queue.
9. The NIC of claim 1 , wherein the circuitry is:
communicatively coupled to the switch fabric and the packet network,
and
configured to modify the at least one egress fabric cell and deliver an egress fabric packet and the egress network packet to the memory.
10. A system, comprising:
a switch fabric;
a packet network;
a first universal network controller (UNIC) communicatively coupled to the switch fabric and the packet network; and
a second UNIC communicatively coupled to the switch fabric and the packet network, wherein the first UNIC comprises:
a bus interface communicatively coupled to a memory within a host computer; and
circuitry configured to:
receive a fabric packet and a network packet from the memory via the bus interface to be transmitted to the second UNIC;
slice the fabric packet into at least one fabric cell; and
queue and schedule the at least one fabric cell and the network packet for transmission of the at least one fabric cell and the network packet over the switch fabric and the packet network, respectively, to the second UNIC,
wherein the circuitry comprises:
an ingress packet processor configured to define at least one virtual output queue (VOQ) in the memory and map at least one destination endpoint to the at least one VOQ; and
an ingress traffic manager configured to queue and de-queue the at least one fabric cell and the network packet in the at least one VOQ,
wherein the circuitry is:
configured to receive at least one egress fabric cell from the switch fabric and an egress network packet from the packet network and map the at least one egress fabric cell and the egress network packet to at least one egress queue, and
configured to manage the at least one egress queue.
11. The system of claim 10 , wherein the circuitry is further configured to determine whether to queue and schedule one or more of the at least one fabric cell and the network packet for unicast or multicast communication over at the switch fabric and the packet network, respectively.
12. The system of claim 10 , wherein the circuitry is further configured to queue and schedule one or more of the at least one fabric cell and the network packet for communication over the switch fabric and the packet network, respectively, based on availability of the switch fabric and the packet network.
13. The system of claim 10 , wherein the circuitry is further configured to produce a switch fabric link and a packet network link based upon respective headers of the fabric packet and the network packet, the switch fabric link defining a first path through the switch fabric to a fabric destination endpoint, and the packet network link defining a second path through the packet network to a network destination endpoint.
14. The system of claim 10 , wherein the circuitry is configured to receive data from the switch fabric and the packet network, respectively, and store the data in the memory.
15. The system of claim 14 , wherein the circuitry is communicatively coupled to an input/output (I/O) interface associated with the host computer by direct memory access.
16. A method of communication, comprising:
receiving a fabric packet and a network packet from a memory within a host computer via a bus interface to be transmitted to at least one external device;
slicing, with a network interface card (NIC), the fabric packet into at least one fabric cell;
queuing and scheduling, with the NIC, the at least one fabric cell and the network packet for transmission of the at least one fabric cell and the network packet over a switch fabric and a packet network, respectively, to the at least one external device;
defining at least one virtual output queue (VOQ) in the memory and mapping at least one destination endpoint to the at least one VOQ;
queuing and de-queuing the at least one fabric cell and the network packet in the at least one VOQ;
receiving at least one egress fabric cell from the switch fabric and an egress network packet from the packet network and mapping the at least one egress fabric cell and the egress network packet to at least one egress queue; and
managing the at least one egress queue.
17. The method of claim 16 , further comprising determining whether to queue and schedule one or more of the at least one fabric cell and the network packet for unicast or multicast communication over the switch fabric and the packet network, respectively.
18. The method of claim 16 , wherein the queuing and scheduling is based on availability of the switch fabric and the packet network.
19. The method of claim 16 , further comprising producing a switch fabric link and a packet network link based upon respective headers of the fabric packet and the network packet, the switch fabric link defining a first path through the switch fabric to a fabric destination endpoint, and the packet network link defining a second path through the packet network to a network destination endpoint.
20. The method of claim 16 , further comprising receiving data from the switch fabric and the packet network, respectively, and storing the data in the memory.
21. The NIC of claim 1 , wherein the circuitry is further configured to receive the fabric packet and the network packet from the memory by direct memory access (DMA) via the bus interface.
22. The NIC of claim 1 , wherein the circuitry is configured to:
define and manage the at least one VOQ virtual output queue (VOQ) in the memory;
map the at least one destination endpoint to the at least one VOQ; and
dequeue data from the at least one VOQ by direct memory access (DMA) via the bus interface.