IP Library Granted Patent US 9,059,083
Granted Patent B2
US 9,059,083 · App. 11/855,712 · Granted Jun 16, 2015

Semiconductor device

Inventors: Henrik Ewe (Burglengenfeld, DE); Joachim Mahler (Regensburg, DE); Manfred Mengel (Bad Abbach, DE); Reimund Engl (Regensburg, DE); Josef Hoeglauer (Munich, DE); Jochen Dangelmaier (Beratzhausen, DE)
Assignee: Infineon Technologies AG
H01L24/25H01L21/4821H01L21/6835H01L23/3107H01L23/49524H01L23/49562H01L23/49575H01L24/24H01L24/82H01L2221/68345H01L2224/24011H01L2224/2402H01L2224/24051H01L2224/24137H01L2224/24226H01L2224/32245H01L2224/76155H01L2224/82001H01L2224/82039H01L2924/01013H01L2924/01015H01L2924/01018H01L2924/01029H01L2924/0103H01L2924/01033H01L2924/01046H01L2924/01047H01L2924/01078H01L2924/01082H01L2924/12044H01L2924/14H01L2924/19043H01L2924/01005H01L2924/01006H01L2924/01068H01L2224/73267H01L2224/82102H01L2224/24145H01L2224/24246H01L2224/32145H01L2225/06568H01L2924/12032
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Quick Facts
Patent No.
US 9,059,083
App. No.
11/855,712
Granted
Jun 16, 2015
Kind
B2
Abstract

A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Claims (26)

1. A semiconductor device comprising:

a carrier;

a semiconductor chip having side faces extending between a top surface and a bottom surface, the bottom surface attached to the carrier;

a structured insulating layer disposed directly on the side faces, the top surface, and a surface of the carrier leaving contacts on the top surface of the semiconductor chip and contact pads on the carrier exposed;

a first conducting line having a first thickness;

a second conducting line having a second thickness; wherein the first thickness is smaller than the second thickness, and wherein the first and second conducting lines are disposed on the structured insulating layer and extend between contacts on the top surface of the semiconductor chip and contact pads on the carrier;

a housing of the semiconductor device comprising a mold material encapsulating the semiconductor chip, the structured insulating layer, and the first and second conducting lines; and

an insulating barrier covering the first conducting line, exposing the second conducting line and being encapsulated by the mold material of the housing.

2. The semiconductor device of claim 1 , further comprising:

a third conducting line deposited over the insulating barrier.

3. The semiconductor device of claim 1 , comprising wherein the carrier is of a TSLP type.

4. The semiconductor device of claim 1 , comprising wherein the carrier is made of an insulating material.

5. The semiconductor device of claim 1 , further comprising:

a mold material encapsulating the semiconductor chip and the first and second conducting lines.

6. The semiconductor device of claim 1 , wherein the first deposited conducting line and the second deposited conducting line are plated metal layers.

7. The semiconductor device of claim 1 , wherein the second conducting line is composed of a base part having substantially the first thickness and a reinforcement part disposed on the based part to obtain the second thickness.

8. The semiconductor device of claim 7 , wherein the first conducting line and the base part of the second conducting line are made of sintered metal particles.

9. The semiconductor device of claim 8 , wherein the reinforcement part of the second conducting line is made of a galvanically deposited metal.

10. A semiconductor device comprising:

a carrier made of metal;

a semiconductor chip having side faces extending between a top surface and a bottom surface, the bottom surface attached to the carrier;

a structured insulating layer disposed directly on the side faces, the top surface, and a surface of the carrier leaving contacts on the top surface of the semiconductor chip and contact pads on the carrier exposed;

a first conducting line disposed directly on the structured insulating layer and extending between a contact on the top surface of the semiconductor chip and a contact pad on the carrier, the first conducting line being disposed directly on at least one contact on the surface of the semiconductor chip and directly on surfaces of the semiconductor chip other than the at least one contact;

an insulating layer applied over the first deposited conducting line;

a second conducting line deposited over the insulating layer; and

a housing of the semiconductor device comprising a mold material encapsulating the semiconductor chip, the structured insulating layer, the first and second conducting lines, and the insulating layer, wherein a thickness of the second conducting line is greater than a thickness of the first conducting line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2007
From: EWE, HENRIK; MAHLER, JOACHIM; MENGEL, MANFRED; ENGL, REIMUND; HOEGLAUER, JOSEF; DANGELMAIER, JOCHEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020151/0165 →
Continuity (1)
Related Publication 20090072379A1 · Mar 19, 2009