IP Library Granted Patent US 9,059,325
Granted Patent B2
US 9,059,325 · App. 14/176,469 · Granted Jun 16, 2015

Semiconductor device and semiconductor device manufacturing method

Inventor: Mitsuaki Kirisawa (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/868H01L29/66128H01L29/861H01L21/324H01L21/265H01L29/7801H01L29/0615H01L29/167
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,059,325
App. No.
14/176,469
Filed
Feb 10, 2014
Granted
Jun 16, 2015
Kind
B2
Art Unit
2823
USPC
257/335
Abstract

In aspects of the invention, an n-type epitaxial layer that forms an n − type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n − type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.

Claims (20)

1. A semiconductor device comprising:

a first conductivity type semiconductor substrate, wherein a dopant of the semiconductor substrate is antimony;

a first conductivity type contact layer, provided on the back surface of the semiconductor substrate, with a concentration higher than that of the semiconductor substrate; and

a first electrode in contact with the contact layer, wherein

the contact layer is doped with phosphorus and includes lattice defects,

the maximum carrier concentration of the contact layer is greater than 1.0×10 18 /cm 3 and less than 5.0×10 19 /cm 3 , and

the diffusion depth of the contact layer from the interface with the first electrode into the semiconductor substrate is 0.5 μm or less;

the semiconductor device further comprising:

a first conductivity type drift layer, provided on the front surface of the semiconductor substrate, with a concentration lower than that of the semiconductor substrate, wherein the total of the thickness of the drift layer and the thickness of the semiconductor substrate is less than 300 μm;

a second conductivity type base region provided in a surface layer on the side of the drift layer opposite to that of the semiconductor substrate; and

a second electrode electrically connected to the base region.

2. The semiconductor device according to claim 1 , wherein the maximum carrier concentration of the contact layer is greater than 3.0×10 18 /cm 3 and less than 1.0×10 19 /cm 3 .

3. The semiconductor device according to claim 1 , wherein the semiconductor substrate is doped with antimony, and the concentration of antimony in the semiconductor substrate is 1.0×10 18 /cm 3 or more, 3.0×10 18 /cm 3 or less.

4. The semiconductor device according to claim 1 , wherein titanium is included in a portion of the first electrode on the side in contact with the contact layer.

5. The semiconductor device according to claim 1 , further comprising:

a first conductivity type source region, provided inside the base region, with a concentration higher than that of the drift layer; and

a gate electrode provided across a dielectric on a portion of the surface of the drift layer sandwiched by the source region and base region.

6. The semiconductor device according to claim 1 , wherein the contact layer includes both a region of higher concentration than that of the semiconductor substrate, and a region of lower concentration region than that of the semiconductor substrate.

7. The semiconductor device according to claim 1 , wherein the semiconductor substrate includes silicon.

8. The semiconductor device according to claim 1 , wherein the contact layer includes antimony.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2014
From: KIRISAWA, MITSUAKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 032266/0866 →
Priority Claims (1)
JP 2011-195969 · Sep 8, 2011 · national
Continuity (2)
Continuation PCTJP2012072822 · Sep 6, 2012
Related Publication 20140159150A1 · Jun 12, 2014