Method and device for implementing cyclic redundancy check codes
The present invention relates to an error control technology in the communication system and discloses a method and an apparatus for implementing Cyclic Redundancy Check (CRC) codes to improve the operation performance of the system significantly and satisfy operation requirements when processing high-rate CRC data. The method includes: performing at least one XOR operation for information bits input in parallel to obtain a first result, where at least one pipeline is added during the XOR operation; performing an XOR operation for a previously obtained CRC code to obtain a second result; and performing an XOR operation for the second result and the first result to obtain a current CRC code. The present invention is applicable to any field that needs to implement CRC codes by means of hardware.
1. A method for implementing Cyclic Redundancy Check (CRC) codes, comprising:
performing at least one Boolean XOR operation for information bits input in parallel to obtain a first result;
adding at least one pipeline for only the information bits during the XOR operation wherein a number of the added pipeline is determined according to a system performance condition comprising a clock frequency change;
performing an XOR operation for a previously obtained CRC code to obtain a second result; and
performing an XOR operation for the second result and the first result to obtain a current CRC code.
2. The method according to claim 1 , further comprising: adding at least one pipeline to the first result.
3. The method according to claim 1 , further comprising: using a CRC code generator polynomial to determine the information bits and CRC codes.
4. An apparatus for implementing Cyclic Redundancy Check (CRC) codes, comprising:
an information bit XOR unit configured to perform at least one Boolean XOR operation for information bits input in parallel to obtain a first result, wherein at least one pipeline is added for only the information bits during the XOR operation wherein a number of added pipeline is determined according to a system performance condition comprising a clock frequency change;
a CRC code XOR unit configured to perform an XOR operation for a previously obtained CRC code to obtain a second result; and
a CRC code obtaining unit configured to perform an XOR operation for the first result obtained by the information bit XOR unit and the second result obtained by the CRC code XOR unit to obtain a current CRC code.
5. The apparatus according to claim 4 , further comprising: a pipelining unit configured to add at least one pipeline to the first result obtained by the information bit XOR unit.