Method and apparatus for decoding memory
View Patent ↗A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.
1. An apparatus comprising:
a first conductive line;
a memory cell directly connected to said first conductive line, said memory cell consisting essentially of a memory element and an ovonic threshold switch (OTS) device;
a first reverse-biased diode directly coupled to said memory cell, said first reverse-biased diode being directly connected to said first conductive line at a first position along said first conductive line, said first reverse biased diode not being contained within a transistor; and
a second reverse-biased diode directly coupled to said memory cell, said second reverse-biased diode being directly connected to said first conductive line at a second position along said first conductive line, said second position differing from said first position.
2. The apparatus of claim 1 , wherein said memory cell and said first reverse-biased diode are coupled in series.
3. The apparatus of claim 1 , wherein said OTS device is a thin-film device.
4. The apparatus of claim 1 , wherein said first reverse-biased diode is a thin-film diode.
5. The apparatus of claim 4 , wherein said thin-film diode comprises silicon.
6. The apparatus of claim 1 , a wherein said memory element is coupled to said OTS device.
7. The apparatus of claim 6 , wherein said memory element is a thin-film memory element.
8. The apparatus of claim 6 , wherein said memory element comprises a phase-change material.
9. The apparatus of claim 6 , wherein said memory element comprises a chalcogenide material.
10. The apparatus of claim 6 , wherein said memory element comprises a variable resistance material.
11. The apparatus of claim 1 , further comprising a first power supply, said first power supply coupled to said memory cell.
12. The apparatus of claim 11 , further comprising a second conductive line, said memory cell coupled between said first power supply and said second conductive line.
13. The apparatus of claim 12 , further comprising a third reverse-biased diode, said third reverse-biased diode coupled to said second conductive line.
14. The apparatus of claim 13 , further comprising a second OTS device, said second OTS device coupled to said second conductive line.
15. The apparatus of claim 14 , further comprising a second power supply, said second OTS device coupled between said second conductive line and said second power supply.
16. The apparatus of claim 13 , wherein said third reverse-biased diode is directly connected to said second conductive line.
17. The apparatus of claim 16 , further comprising a fourth reverse-biased diode directly connected to said second conductive line, said third reverse-biased diode and said fourth reverse-biased diode directly connecting said second conductive line at different positions.
18. The apparatus of claim 1 , wherein said second reverse biased diode is not contained within a transistor.
19. An apparatus comprising:
a first conductive line;
a memory cell directly connected to said first conductive line, said memory cell consisting essentially of a memory element and an ovonic threshold switch (OTS) device;
a first reverse-biased diode directly coupled to said memory cell, said first reverse-biased diode being directly connected to said first conductive line at a first position along said first conductive line; and
a second reverse-biased diode directly coupled to said memory cell, said second reverse-biased diode being directly connected to said first conductive line at a second position along said first conductive line, said second position differing from said first position;
wherein said apparatus lacks direct connection of a transistor to said first position.
20. The apparatus of claim 19 , wherein said apparatus lacks direction connection of a transistor to said second position.
21. The apparatus of claim 19 , wherein said memory cell and said first reverse-biased diode are coupled in series.
22. The apparatus of claim 19 , wherein said OTS device is a thin-film device.
23. The apparatus of claim 19 , wherein said first reverse-biased diode is a thin-film diode.
24. The apparatus of claim 23 , wherein said thin-film diode comprises silicon.
25. The apparatus of claim 19 , a wherein said memory element is coupled to said OTS device.
26. The apparatus of claim 25 , wherein said memory element is a thin-film memory element.
27. The apparatus of claim 25 , wherein said memory element comprises a phase-change material.
28. The apparatus of claim 25 , wherein said memory element comprises a chalcogenide material.
29. The apparatus of claim 25 , wherein said memory element comprises a variable resistance material.
30. The apparatus of claim 19 , further comprising a first power supply, said first power supply coupled to said memory cell.
31. The apparatus of claim 30 , further comprising a second conductive line, said memory cell coupled between said first power supply and said second conductive line.
32. The apparatus of claim 31 , further comprising a third reverse-biased diode, said third reverse-biased diode coupled to said second conductive line.
33. The apparatus of claim 32 , further comprising a second OTS device, said second OTS device coupled to said second conductive line.
34. The apparatus of claim 33 , further comprising a second power supply, said second OTS device coupled between said second conductive line and said second power supply.
35. The apparatus of claim 32 , wherein said third reverse-biased diode is directly connected to said second conductive line.
36. The apparatus of claim 35 , further comprising a fourth reverse-biased diode directly connected to said second conductive line, said third reverse-biased diode and said fourth reverse-biased diode directly connecting said second conductive line at different positions.