Semiconductor device and method of fabricating the same

1. A semiconductor device comprising:

a semiconductor substrate having a P-type region and at least one surface with integrated circuits formed thereon;

at least one via electrode extending in the semiconductor substrate;

a dielectric layer formed between the semiconductor substrate and the at least one via electrode, the dielectric layer including a first portion, and a second portion that faces the P-type region of the semiconductor substrate;

an N-type region formed in the semiconductor substrate to contact the first portion of the dielectric layer; and

a power circuit, which is electrically connected to the N-type region and applies a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the p-type region of semiconductor substrate facing the second portion of the dielectric layer.

2. The semiconductor device of claim 1 , wherein the P-type region of the semiconductor substrate includes an entire body, wells, pockets, halos, or a combination thereof.

3. The semiconductor device of claim 1 , wherein the at least one via electrode is formed in an active region of the semiconductor substrate.

4. The semiconductor device of claim 1 , wherein the at least one via electrode includes a conductive material chosen from doped poly-silicon, tungsten, aluminum, copper, gold, silver, tantalum, titanium, molybdenum, cobalt, nickel, platinum, and palladium, an alloy of the conductive material, a conductive nitride of the conductive material, a conductive metal oxide of the conductive material, a conductive silicide of the conductive material, or carbon.

5. The semiconductor device of claim 1 , wherein a cross-sectional plane of the at least one via electrode has a circular shape, an elliptical shape, a polygonal shape, or a combination thereof, wherein the cross-sectional plane is parallel to a main surface of the semiconductor substrate.

6. The semiconductor device of claim 1 , wherein the N-type region comprises a highly-doped impurity region which has an impurity concentration higher than that of the semiconductor substrate and has a first depth.

7. The semiconductor device of claim 6 , wherein the N-type region further comprises a lightly-doped impurity region arranged below the highly-doped impurity region,

wherein the lightly-doped impurity region has an impurity concentration lower than the impurity concentration of the highly-doped impurity region, and

wherein the lightly-doped impurity region has a second depth greater than the first depth.

8. The semiconductor device of claim 1 , wherein the N-type region is shared by at least two via electrodes.

9. The semiconductor device of claim 1 , wherein the integrated circuits are formed on a top surface of the semiconductor substrate, and

wherein the N-type region is formed at a bottom surface of the semiconductor substrate.

10. The semiconductor device of claim 1 , wherein the bias voltage has a voltage level such that a parasitic PN diode formed between the P-type region and the N-type region has a reverse driving mode.

11. The semiconductor device of claim 1 , wherein signals present in the at least one via electrode are 0V voltage signals or positive voltage signals, and the power circuit is grounded.

12. The semiconductor device of claim 1 , wherein the N-type region partially surrounds a portion of a sidewall of the dielectric layer.

13. The semiconductor device of claim 1 , wherein the at least one via electrode and the integrated circuits share the active region.

14. The semiconductor device of claim 1 , wherein the dielectric layer comprises a silicon oxide layer or a high-k thin film.