Current-balancing in interleaved circuit phases using a parameter common to the phases
A method for balancing an electrical parameter (e.g, a current or a voltage) between phases in a multi-phase interleaved circuit includes sensing the electrical parameter, demultiplexing the electrical parameter in accordance with a phase-select signal, sampling the demultiplexed components into a plurality of digital signals, generating an error signal based on a difference between the digital signals, and modulating the phase-select signal, as applied to the phases, in accordance with the error signal.
1. A method for balancing phases in a multi-phase interleaved circuit, the method comprising:
sensing an electrical parameter for each of multiple signal phases using a sense element that is common to the circuit phases;
demultiplexing the electrical parameter, in accordance with a phase-select signal, into demultiplexed signal components that respectively correspond to the multiple signal phases;
sampling the demultiplexed signal components into a plurality of digital signals that respectively correspond to the multiple signal phases;
generating an error signal using a digital integrator to integrate a difference between the digital signals; and
modulating the phase-select signal, as applied to the circuit phases, in accordance with the generated error signal.
2. The method of claim 1 , wherein sensing the electrical parameter includes sensing a current signal for each of the multiple signal phases using the sense element.
3. The method of claim 1 , wherein the sensing the electrical parameter includes sensing a voltage signal for each of the multiple signal phases using the sense element.
4. The method of claim 2 , wherein generating the error signal comprises applying a scaling factor to a result of the integration.
5. The method of claim 4 , further comprising applying a first scaling factor when a duty cycle of the phase-select signal is less than 50% and applying a second scaling factor when the duty cycle of the phase-select signal is greater than 50%.
6. The method of claim 4 , wherein the generating the error signal comprises applying a duty-cycle-dependent scaling factor to the result of the integration.
7. The method of claim 1 , wherein demultiplexing the electrical parameter comprises dividing the electrical parameter into two 180 degree sections.
8. The method of claim 1 , wherein modulating the phase select signal comprises modifying the phase-select signal as applied to only one circuit phase.
9. The method of claim 1 , wherein modulating the phase select signal comprises modifying the phase-select signal as applied to more than one circuit phase.
10. The method of claim 1 , wherein sensing the electrical parameter comprises sensing a voltage across a resistor.
11. A system for balancing phases in a multi-phase interleaved circuit, the system comprising:
a demultiplexer for dividing an input signal into a plurality of demultiplexed signals in accordance with a phase-select signal, the input signal being an electrical parameter sensed using a sense element that is common to the circuit phases;
an analog-to-digital converter circuit for converting the demultiplexed signals into a plurality of respective digital signals;
a comparator for detecting a difference between the plurality of digital signals;
an integrator that receives information about the detected difference between the plurality of digital signals and, in response, provides an integration signal; and
a modulator for modulating the phase-select signal in accordance with an error signal that is based at least in part on the integration signal.
12. The system of claim 11 , wherein the electrical parameter is a current or a voltage that is sensed using the sense element.
13. The system of claim 11 , wherein the integrator comprises a reset input that, when activated, zeroes the integrator.
14. The system of claim 11 , wherein the analog-to-digital converter circuit comprises a plurality of analog-to-digital converters.
15. The system of claim 14 , wherein each analog-to-digital converter comprises a sigma-delta analog-to-digital converter.
16. The system of claim 11 , wherein the circuit phases comprise two circuit phases.
17. The system of claim 11 , wherein the multi-phase interleaved circuit comprises a multi-phase power-factor correction circuit.
18. The system of claim 11 , further comprising a scaler for applying a scaling factor to the integration signal prior to its use by the modulator.
19. The system of claim 18 , wherein the scaler is configured to apply a duty-cycle-dependent scaling factor to the integration signal prior to its use by the modulator.