IP Library Granted Patent US 9,086,874
Granted Patent B2
US 9,086,874 · App. 13/491,353 · Granted Jul 21, 2015

Above motherboard interposer with quarter wavelength electrical paths

Inventors: Morgan Johnson (Portland, OR); Frederick G. Weiss (Newberg, OR)
Assignee: Morgan/Weiss Technologies Inc.
G06F1/32H01L23/32H05K1/0243H01L2924/0002H05K1/141H05K1/189H05K2201/10159H05K2201/10189H05K2201/10378H05K2201/10515Y10T29/4913
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Quick Facts
Patent No.
US 9,086,874
App. No.
13/491,353
Granted
Jul 21, 2015
Kind
B2
Abstract

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

Claims (9)

1. A computing device, comprising:

a circuit substrate having a socket;

a main processor having a clock frequency;

an interposer substrate inserted between the socket and the main processor, the interposer substrate having a first set of interconnects that electrically connect between the socket and circuits on the circuit substrate, and a second set of interconnects that electrically connect to the main processor without connecting to the socket or the circuit substrate; and

peripheral circuit modules residing on the interposer substrate, the interposer substrate having conductive traces between the peripheral circuit modules and the main processor, where the conductive traces have a length in meters of less than one-quarter a distance determined by three hundred divided by the clock frequency of the main processor expressed in Megahertz.

2. The computing device of claim 1 , wherein the interposer substrate has multiple connections, such that path lengths between the main processor and each connection are equal.

3. The computing device of claim 2 , wherein the interposer substrate is folded.

4. The computing device of claim 2 , wherein the interposer substrate comprises a multi-layer substrate resulting from the interposer substrate being folded multiple times.

5. The computing device of claim 4 , wherein the peripheral circuit modules are stacked.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2021
From: MORGAN/WEISS TECHNOLOGIES, INC.
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 055450/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2013
From: JOHNSON, MORGAN; WEISS, FREDERICK G.
To: MORGAN/WEISS TECHNOLOGIES INC.
Reel/Frame 030770/0210 →
Continuity (3)
Continuation 13163502 · Jun 17, 2011
Provisional Application 61476501 · Apr 18, 2011
Related Publication 20120262862A1 · Oct 18, 2012