Successive approximation analog to digital converter and method of analog to digital conversion
An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
1. A method of analog to digital conversion of an analog to digital converter including a digital-to analog converting circuit, the method comprising:
sampling and holding an analog input signal;
converting digital output data to an analog signal to generate a hold voltage signal;
comparing the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal; and
performing successive approximation based on the comparison output voltage signal to generate the digital output data,
wherein the performing successive approximation to generate the digital output data comprises:
demultiplexing the comparison output voltage signal to generate a first voltage signals in response to a selecting signal; and
latching and outputting one of the first voltage signals in response to each bit of a conversion control signal in response to each bit of a conversion control signal.
2. The method of claim 1 , wherein generating a comparison output voltage signal comprises:
comparing the hold voltage signal with the reference voltage signal in response to a first clock signal to generate a first comparison output voltage signal; and
comparing the hold voltage signal with the reference voltage signal in response to a second clock signal having a phase opposite to a phase of the first clock signal to generate a second comparison output voltage signal.
3. The method of claim 2 , wherein the comparison output voltage signal is a signal in which the first comparison output voltage signal and the second comparison output voltage signal are added alternately.
4. The method of claim 1 , wherein the conversion control signal is generated based on the clock signal and a conversion start signal.
5. The method of claim 1 , wherein generating the differential output voltage signals comprises:
amplifying a difference between the hold voltage signal and the reference voltage signal to generate first differential output voltage signals; and
amplifying a difference between the hold voltage signal and the reference voltage signal to generate second differential output voltage signals.
6. A method of analog to digital conversion of an analog to digital converter including a digital-to analog converting circuit, the method comprising:
sampling and holding an analog input signal;
converting digital output data to an analog signal to generate a hold voltage signal;
amplifying a difference between the hold voltage signal and a reference voltage signal to generate differential output voltage signals using a preamplifier;
comparing the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal; and
performing successive approximation based on the comparison output voltage signal to generate the digital output data,
wherein the performing successive approximation to generate the digital output data comprises:
demultiplexing the comparison output voltage signal to generate a first voltage signals in response to a selecting signal; and
latching and outputting one of the first voltage signals in response to each bit of a conversion control signal in response to each bit of a conversion control signal.
7. The method of claim 6 , wherein generating a comparison output voltage signal comprises:
comparing the differential output voltage signals of the preamplifier with each other in response to a first clock signal to generate a first comparison output voltage signal; and
comparing the differential output voltage signals of the preamplifier with each other in response to a second clock signal having a phase opposite to a phase of the first clock signal to generate a second comparison output voltage signal.
8. The method of claim 7 , wherein the comparison output voltage signal is a signal in which the first comparison output voltage signal and the second comparison output voltage signal are added alternately.
9. The method of claim 6 , wherein generating the differential output voltage signals using the preamplifier is configured to decrease an offset voltage of the comparison output voltage signal.
10. The method of claim 6 , wherein generating the differential output voltage signals using the preamplifier is configured to reduce noise of an output terminal of the digital to analog converting circuit.