IP Library Granted Patent US 9,146,871
Granted Patent B2
US 9,146,871 · App. 13/995,283 · Granted Sep 29, 2015

Retrieval of previously accessed data in a multi-core processor

Inventors: Simon C. Steely, Jr. (Hudson, NH); William C. Hasenplaugh (Boston, MA); Joel S. Emer (Hudson, MA)
Assignee: Intel Corporation
G06F12/0822G06F12/0817G06F12/0846G06F13/00G06F13/10G06F13/385
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Quick Facts
Patent No.
US 9,146,871
App. No.
13/995,283
Granted
Sep 29, 2015
Kind
B2
Abstract

A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.

Claims (39)

1. A processor comprising:

a requester to send a memory request, the memory request having a memory address of a memory that stores requested data;

a record keeping structure to receive the memory request;

circuitry to determine a last accessor of the memory address;

circuitry to send a cache probe to the last accessor;

circuitry to determine the last accessor no longer has a copy of the line; and

circuitry to send a request for previously accessed version of the line, the request bypassing the tag-directories and obtaining the requested data from memory.

2. The processor of claim 1 , wherein the processor is a multi-core processor and the record keeping structure is oblivious that the latest value of the requested data is retrieved from the memory.

3. The processor of claim 2 , wherein the requester is a core and the last accessor is another core of the multi-core processor.

4. The processor of claim 3 , wherein the requester and last accessor belong to a same processing unit domain of the multi-core processor.

5. The processor of claim 3 , wherein the requester and last accessor belong to different processing unit domains of the multi-core processor.

6. The processor of claim 1 , wherein the record keeping structure is a tag directory.

7. The processor of claim 1 , wherein the record keeping structure is a hierarchy of tag directories.

8. A method comprising:

sending a memory request from a requester to a record keeping structure, the memory request having a memory address of a memory that stores requested data;

determining, by the record keeping structure, a last accessor of the memory address;

sending, by the record keeping structure, a cache probe to the last accessor;

determining the last accessor no longer has a copy of the line; and

sending a request for previously accessed version of the line, the request bypassing the tag-directories and obtaining the requested data from memory.

9. The method of claim 8 , wherein the requester is a core and the last accessor is another core of a multi-core processor, and the record keeping structure is oblivious that the latest value of the requested data is retrieved from the memory.

10. The method of claim 9 , wherein the requester and last accessor belong to a same processing unit domain of the multi-core processor.

11. The method of claim 9 , wherein the requester and last accessor belong to different processing unit domains of the multi-core processor.

12. The method of claim 8 , wherein the record keeping structure is a tag directory of a multi-core processor.

13. The method of claim 8 , wherein the record keeping structure is a hierarchy of tag directories of a multi-core processor.

14. A system comprising:

a memory;

a processor coupled to the memory for executing computer instructions stored therein, the processor including:

a requester to send a memory request, the memory request having a memory address of a memory that stores requested data;

a record keeping structure to receive the memory request;

circuitry to determine a last accessor of the memory address;

circuitry to send a cache probe to the last accessor;

circuitry to determine the last accessor no longer has a copy of the line; and

circuitry to send a request for previously accessed version of the line, the request bypassing the tag-directories and obtaining the requested data from memory.

15. The system of claim 14 , wherein the processor is a multi-core processor and the record keeping structure is oblivious that the latest value of the requested data is retrieved from the memory.

16. The system of claim 15 , wherein the requester is a core and the last accessor is another core of the multi-core processor.

17. The system of claim 16 , wherein the requester and last accessor belong to a same processing unit domain of the multi-core processor.

18. The system of claim 16 , wherein the requester and last accessor belong to different processing unit domains of the multi-core processor.

19. The system of claim 14 , wherein the record keeping structure is a tag directory of a multi-core processor.

20. The system of claim 14 , wherein the record keeping structure is a hierarchy of tag directories of a multi-core processor.

Continuity (1)
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