Memory array device and method for reducing read current of the same

1. A memory array device comprising a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays;

wherein each subsidiary memory array includes:

a memory unit for storing a data;

a programming indication bit arranged prior to the memory unit for indicating whether the subsidiary memory array has been programmed; and

an inversion indication bit arranged subsequent to the memory unit for indicating whether a data had been inverted before being written in the memory unit of the subsidiary memory array.

2. The memory array device according to claim 1 , wherein the programming indication bit having a value of 0 indicates that the corresponding subsidiary memory array has been programmed, and wherein the programming indication bit having a value of 1 indicates that the corresponding subsidiary memory array has not been programmed.

3. The memory array device according to claim 1 , wherein the inversion indication bit having a value of 0 indicates that the data had been inverted before being written in the memory unit of the subsidiary memory array, and wherein the inversion indication bit having a value of 1 indicates that the data had not been inverted before being written in the memory unit of the subsidiary memory array.

4. A method for reducing a read current of a memory array device, comprising the following steps:

providing a memory array device comprising a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays, each subsidiary memory array including a memory unit for storing a data;

arranging a programming indication bit prior to the memory unit and an inversion indication bit subsequent to the memory unit of each subsidiary memory array;

programming one or more subsidiary memory arrays of the memory array device, including:

setting the inversion indication bit of a currently programming subsidiary memory array to a certain value following a predetermined rule; and

setting the programming indication bit of the currently programming subsidiary memory array to a value which indicates that the subsidiary memory array has been programmed;

writing both a data or an inversion of the data, according to the set value of the inversion indication bit, and the set value of the inversion indication bit in the programmed subsidiary memory array; and

reading one or more subsidiary memory arrays of the memory array device, including:

reading the programming indication bit of a currently reading subsidiary memory array to determine whether the subsidiary memory array has been programmed, and outputting ‘1’ if the subsidiary memory array has not been programmed.

5. The method according to claim 4 ,

wherein reading one or more subsidiary memory arrays of the memory array device further including:

if the subsidiary memory array has been programmed, reading out the stored data subsequent to the programming indication bit, checking the inversion indication bit of the subsidiary memory array, and outputting the stored data or an inversion of the stored data based on the value of the inversion indication bit of the subsidiary memory array.

6. The method according to claim 5 , wherein outputting the stored data or an inversion of the stored data based on the value of the inversion indication bit of the subsidiary memory array includes:

outputting the stored data if the value of the inversion indication bit indicates that the data had not been inverted before being written in the memory unit of the subsidiary memory array; or

outputting an inversion of the stored data if the value of the inversion indication bit indicates that the data had been inverted before being written in the memory unit of the subsidiary memory array.

7. The method according to claim 4 , wherein the predetermined rule is that,

if a number of bits, having a value of 1, of a data to be written in a currently programming subsidiary memory array reaches or exceeds half of a total number of bits of the data, the inversion indication bit of the subsidiary memory array is set to a value indicating that the data had been inverted before being written in the memory unit of the subsidiary memory array, and an inversion of the data and the set value of the inversion indication bit are written in the subsidiary memory array; or

if a number of bits, having a value of 1, of the data to be written in a currently programming subsidiary memory array is smaller than half of a total number of bits of the data, the inversion indication bit of the subsidiary memory array is set to a value indicating that the data had not been inverted before being written in the memory unit of the subsidiary memory array, and the data and the set value of the inversion indication bit are written in the subsidiary memory array.

8. The method according to claim 7 , wherein if the number of bits, having a value of 1, of the data to be written in the currently programming subsidiary memory array reaches or exceeds half of the total number of bits of the data, the value of the inversion indication bit is set to 0, otherwise to 1.

9. The method according to claim 4 , wherein the programming indication bit of the subsidiary memory array is set to 0 to indicate that the subsidiary memory array has been programmed.