ESD robust level shifter

1. An inverter type level shifter comprising:

a first power supply voltage and a first ground voltage;

a first inverter operating on the first power supply voltage and the first ground voltage to generate a first inverter output in response to an input signal, the first inverter comprising:

a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor; and

a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor; wherein a drain of the blocking NMOS transistor and a drain of the blocking PMOS transistor are interconnected to generate the first inverter output;

a second power supply voltage and a second ground voltage; and

a second inverter coupled to the first inverter output and operating on the second power supply voltage and the second ground voltage to generate an output signal; wherein the blocking PMOS transistor provides the additional blocking on an event of a voltage spike in the second power supply voltage with respect to the first power supply voltage, and the blocking NMOS transistor provides the additional blocking on an event of a voltage spike in the second ground domain with respect to the first ground domain, to increase electro-static discharge (ESD) protection robustness to the second inverter, and wherein a bulk terminal of the blocking PMOS transistor is connected to the drain of the blocking PMOS transistor such that the blocking PMOS transistor provides the additional voltage drop in the path on the event of the voltage spike in the second power supply voltage with respect to the first power supply voltage.

2. The inverter type level shifter of claim 1 , wherein a bulk terminal and drain of the blocking NMOS transistor are interconnected such that the blocking NMOS transistor provides the additional voltage drop in the path on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

3. The inverter type level shifter of claim 2 , wherein the blocking NMOS transistor increases the damage threshold of the gate oxide of the NMOS transistor in the second inverter.

4. The inverter type level shifter of claim 1 , wherein gates of the first PMOS transistor, blocking PMOS transistor, blocking NMOS transistor and the first NMOS transistor are interconnected and are configured to receive the input signal.

5. The inverter type level shifter of claim 1 , wherein the second inverter comprises a second PMOS transistor coupled to a second NMOS transistor.

6. The inverter type level shifter of claim 1 receives the input signal to generate the output signal with a voltage level according to the level of the input signal, wherein the input signal operates between the first power supply voltage and the first ground voltage, and the output signal operates between the second power supply voltage and the second ground voltage.

7. The inverter type level shifter of claim 1 , wherein the blocking PMOS and blocking NMOS are implemented as equivalent diode to provide ESD robustness.

8. An inverter type level shifter comprising:

a first power supply voltage, a second power supply voltage and a ground voltage;

a first inverter operating on the first power supply voltage and the ground voltage to generate a first inverter output in response to an input signal; the first inverter comprising:

a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor; and

a first NMOS transistor having a drain coupled to a drain of the blocking PMOS transistor to generate the first inverter output; and

a second inverter coupled to the first inverter output and operating on the second power supply voltage and the ground voltage; to generate an output signal; wherein the blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage with respect to the first power supply voltage, to increase electro-static discharge (ESD) protection robustness of the second inverter, and wherein a bulk terminal and the drain of the blocking PMOS transistor are interconnected, such that the blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage with respect to the first power supply voltage.

9. The inverter type level shifter of claim 8 , wherein gates of the first PMOS transistor, the first NMOS transistor and the blocking PMOS transistor are interconnected and are configured to receive the input signal.

10. The inverter type level shifter of claim 8 , wherein the second inverter comprises a second PMOS transistor coupled to a second NMOS transistor.

11. The inverter type level shifter of claim 8 receives the input signal to generate the output signal with a voltage level according to the level of the input signal, wherein the input signal operates between the first power supply voltage and the ground voltage, and the output signal operates between the second power supply voltage and the ground voltage.

12. The inverter type level shifter of claim 8 , wherein the blocking PMOS is implemented as equivalent diode to provide ESD robustness.