Wafer-level light emitting diode structure, light emitting diode chip, and method for forming the same
A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.
1. A method for fabricating a wafer-level light emitting diode structure, comprising:
providing a growth substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate;
subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a plurality of first portions and a plurality of second portions, wherein each of the plurality of second portions has a stacked structure and each of the plurality of first portions has an extended portion of the first semiconductor layer, wherein the plurality of first portions overlap with predetermined cutting ranges;
forming an first electrode on the extended portion of the first semiconductor layer in each of the plurality of first portions;
forming a second electrode on the stacked structure in each of the plurality of second portions;
measuring a current-voltage characteristic of the wafer-level light emitting diode structure via the first electrode and the second electrode; and
cutting the growth substrate along the predetermined cutting ranges, thus removing each first electrode and obtaining a plurality of light emitting diode chips.
2. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 1 , before cutting the growth substrate along the predetermined cutting ranges, further comprising:
measuring a driving voltage of the wafer-level light emitting diode structure via the first electrode and the second electrode.
3. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 1 , before cutting the growth substrate along the predetermined cutting ranges, further comprising:
measuring a spectrum characteristic of the wafer-level light emitting diode structure via the first electrode and the second electrode.
4. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 1 , before cutting the growth substrate along the predetermined cutting ranges, further comprising:
classifying or marking the wafer-level light emitting diode according to a result of the step of measuring the current-voltage characteristic of the wafer-level light emitting diode structure.
5. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 4 , before cutting the growth substrate along the predetermined cutting ranges, further comprising:
forming a passivation layer to cover a side wall of the patterned second semiconductor layer, a side wall of the patterned emitting layer, and a side wall of the patterned first semiconductor layer.
6. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 4 , wherein a width of the each predetermined cutting range is less than or equal to the first portion.
7. The method for fabricating a wafer-level light emitting diode structure as claimed in claim 4 , wherein two of the predetermined cutting ranges are respectively located on opposite sides of the first electrode.
8. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 1 , wherein the first electrode is within or out of each predetermined cutting range.
9. A method for fabricating a wafer-level light emitting diode structure, comprising:
providing a growth substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate;
subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a plurality of first portions and a plurality of second portions, wherein each of the plurality of second portions has a stacked structure and each of the plurality of first portions has an extended portion of the first semiconductor layer, wherein the plurality of first portions overlap with predetermined cutting ranges;
forming an first electrode on the extended portion of the first semiconductor layer in each of the plurality of first portions;
forming a second electrode on the stacked structure in each of the plurality of second portions;
measuring photoelectric properties of the wafer-level light emitting diode structure via the first electrode and the second electrode; and
cutting the growth substrate along the predetermined cutting ranges, thus removing each first electrode and obtaining a plurality of light emitting diode chips.
10. The method for fabricating the wafer-level light emitting diode structure as claimed in claim 9 , wherein the photoelectric properties comprise a current-voltage characteristic, driving voltage, or spectrum characteristic.
11. A method for fabricating a wafer-level light emitting diode structure, comprising:
providing a growth substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate;
subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a plurality of first depressed portions and a plurality of second depressed portions, wherein each of the plurality of second depressed portions has a stacked structure and each of the plurality of first depressed portions has an extended portion of the first semiconductor layer, wherein the plurality of first depressed portions overlap with predetermined cutting ranges;
forming an first electrode on the extended portion of the first semiconductor layer in each of the plurality of first depressed portions;
forming a second electrode on the stacked structure in each of the plurality of second depressed portions;
measuring photoelectric properties of the wafer-level light emitting diode structure via the first electrode and the second electrode; and
cutting the growth substrate along the predetermined cutting ranges, thus removing each first electrode and obtaining a plurality of light emitting diode chips.