Folded FIFO memory generator
Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.
1. A method, comprising:
receiving a request to store a first data portion in a first-in first-out (FIFO) memory, wherein the FIFO memory includes a memory element comprising a plurality of rows and has depth and width dimensions that differ from depth and width dimensions of the FIFO memory, and a buffer that is sized to store a single row of the memory element;
storing the first data portion in the buffer in the FIFO memory;
receiving a request to store a second data portion in the FIFO memory;
determining that storing the second data portion in the buffer would exceed a capacity of the buffer; and
transferring the contents of the buffer into a single row of the memory element in the FIFO memory, wherein each row in the memory element is sized to store multiple data portions.
2. The method of claim 1 , further comprising:
receiving a read request to retrieve a stored data portion from the FIFO memory;
determining whether the stored data portion is within the buffer or within the memory element;
if the stored data portion is within the buffer, retrieving the stored data portion from the buffer without accessing the memory element; or
if the stored data portion is within the memory element, retrieving the stored data portion from the memory element without accessing the buffer.
3. The method of claim 2 , wherein the stored data portion is not deleted when read from the buffer or memory element.
4. The method of claim 1 , wherein a total number of rows in the memory element is less than a total depth of the FIFO memory.
5. The method of claim 1 , wherein a row width of the memory element is selected by altering depth and width dimensions of the FIFO memory until the width dimension corresponding to the altered dimensions is less than or equal to a minimum width threshold.
6. The method of claim 1 , wherein the memory element comprises a random access memory (RAM), and wherein the first data portion is stored in one or more memory cells of the RAM.
7. The method of claim 1 , further comprising:
receiving a simultaneous read request and write request to the same memory address:
routing a third data portion associated with the simultaneous read request and write request to an output of the FIFO memory via a data path that bypasses the buffer and the memory element; and
storing the third data portion in the buffer, wherein the third data portion is simultaneously routed via the data path and stored in the buffer.
8. The method of claim 1 , further comprising storing the second data portion in the buffer in the FIFO memory simultaneously with transferring the contents of the buffer into the single row of the memory element.
9. The method of claim 1 , further comprising:
receiving a request to store a third data portion in the FIFO memory;
determining that storing the third data portion in the buffer would exceed a capacity of the buffer;
determining that transferring the contents of the buffer into the memory element in the FIFO memory would exceed a capacity of the memory element; and
stalling the third request to store the third data portion in the FIFO memory.
10. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to:
receive a request to store a first data portion in a first-in first-out (FIFO) memory, wherein the FIFO memory includes a memory element comprising a plurality of rows and has depth and width dimensions that differ from depth and width dimensions of the FIFO memory, and a buffer that is sized to store a single row of the memory element;
store the first data portion in the buffer in the FIFO memory;
receive a request to store a second data portion in the FIFO memory;
determine that storing the second data portion in the buffer would exceed a capacity of the buffer; and
transfer the contents of the buffer into a single row of the memory element in the FIFO memory, wherein each row in the memory element is sized to store multiple data portions.
11. The non-transitory computer-readable storage medium of claim 10 , further comprising computer-readable program code configured to:
receive a read request to retrieve a stored data portion from the FIFO memory;
determine whether the stored data portion is within the buffer or within the memory element;
if the stored data portion is within the buffer, retrieve the stored data portion from the buffer without accessing the memory element; or
if the stored data portion is within the memory element, retrieve the stored data portion from the memory element without accessing the buffer.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the stored data portion is not deleted when read from the buffer or memory element.
13. The non-transitory computer-readable storage medium of claim 10 , wherein a total number of rows in the memory element is less than a total depth of the FIFO memory.
14. The non-transitory computer-readable storage medium of claim 10 , wherein a row width of the memory element is selected by altering depth and width dimensions of the FIFO memory until the width dimension corresponding to the altered dimensions is less than or equal to a minimum width threshold.
15. The non-transitory computer-readable storage medium of claim 10 , wherein the memory element comprises a random access memory (RAM), and wherein the first data portion is stored in one or more memory cells of the RAM.
16. A FIFO memory, comprising:
a memory element comprising a plurality of rows and coupled to a buffer, wherein each row in the memory element is sized to store multiple data portions, and wherein the memory element has depth and width dimensions that differ from depth and width dimensions of the FIFO;
the buffer for storing a plurality of data portions associated with write requests received by the FIFO memory, wherein the buffer is sized to store a single row of the memory element; and
routing logic configured to determine that storing a next data portion in the buffer would exceed a capacity of the buffer and transfer the contents of the buffer into a single row of the memory element.
17. The FIFO memory of claim 16 , further comprising
selection logic configured to, in response to a read request to retrieve a stored data portion:
determine whether the stored data portion is within the buffer or within the memory element;
if the stored data portion is within the buffer, retrieve the stored data portion from the buffer without accessing the memory element; or
if the stored data portion is within the memory element, retrieve the stored data portion from the memory element without accessing the buffer.
18. The FIFO memory of claim 17 , wherein the selection logic comprises a delayed buffer disposed in a data path between the buffer and an output of the FIFO memory, and the delayed buffer is configured to store the stored data portion retrieved from the buffer before the stored data portion is output from the FIFO memory.
19. The FIFO memory of claim 17 , wherein the selection logic comprises a multiplexer disposed in a data path between the memory element and an output of the FIFO memory, and the multiplexer is configured to select the stored data portion from a plurality of data portions stored within a row of the memory element.
20. The FIFO memory of claim 16 , wherein a total number of rows in the memory element is less than a total depth of the FIFO memory.
21. The FIFO memory of claim 16 , wherein a row width of the memory element is selected by altering depth and width dimensions of the FIFO memory until the width dimension corresponding to the altered dimensions is less than or equal to a minimum width threshold.
22. The FIFO memory of claim 16 , wherein the memory element comprises a random access memory (RAM), and wherein the first data portion is stored in one or more memory cells of the RAM.