IP Library Granted Patent US 9,190,341
Granted Patent B2
US 9,190,341 · App. 13/489,297 · Granted Nov 17, 2015

Lidded integrated circuit package

Inventor: Dwayne Richard Shirley (Dallas, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L23/3735B32B37/12B32B37/18H01L23/06H01L23/3675B32B2457/00H01L2224/16225H01L2224/32225H01L2224/73204H01L2224/73253H01L2924/15311H01L2924/16152
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Quick Facts
Patent No.
US 9,190,341
App. No.
13/489,297
Granted
Nov 17, 2015
Kind
B2
Abstract

A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.

Claims (29)

1. A lidded integrated circuit (IC) package comprising:

a lid having a heat conductive substrate;

a native silicon oxide layer connected to said heat conductive substrate by at least one intermediate layer; and

a crystallized amorphous silicon film layer disposed between said heat conductive substrate and said native silicon oxide layer.

2. The lidded integrated circuit (IC) package of claim 1 , wherein said lid further comprises:

a nickel layer disposed between said heat conductive substrate and said native silicon oxide layer.

3. The lidded integrated circuit (IC) package of claim 1 , further comprising:

a semiconductor die having a top surface and a bottom surface; and

a layer of thermal interface material attached to said top surface of said semiconductor die and to said native silicon oxide layer.

4. The lidded integrated circuit (IC) package of claim 3 , wherein said lid comprises a central body portion which comprises said native silicon oxide layer, and a peripheral flange portion; and

further comprising:

an electrical connection substrate, wherein said peripheral flange is connected to said electrical connection substrate.

5. The lidded integrated circuit (IC) package of claim 3 , wherein said semiconductor die is mounted on said electrical connection substrate.

6. The lidded integrated circuit (IC) package of claim 3 , wherein said thermal interface material comprises at least one of silicone and epoxy.

7. The lidded integrated circuit (IC) package of claim 1 , wherein said lid comprises:

a central body portion and a peripheral flange portion, and

further comprising:

a semiconductor die having a top surface and a bottom surface;

a layer of thermal interface material attached to said top surface of said semiconductor die and to said native silicon oxide layer; and

an electrical connection substrate, wherein said peripheral flange of said lid is connected to said electrical connection substrate.

8. The lidded integrated circuit (IC) package of claim 7 , further comprising:

a PC board operatively connected to said electrical connection substrate; and

a heatsink mounted on and which is operatively connected to said lid.

9. A lidded integrated circuit (IC) package comprising:

a lid having a copper substrate;

a nickel layer deposited on said copper substrate;

a crystallized amorphous silicon layer deposited on said nickel layer; and

a native silicon oxide layer connected to said copper substrate by at least one intermediate layer.

10. The lidded integrated circuit (IC) package of claim 9 , wherein said native silicon oxide layer is formed on said crystallized amorphous silicon layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2012
From: SHIRLEY, DWAYNE RICHARD
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 028363/0925 →
Continuity (1)
Related Publication 20130320517A1 · Dec 5, 2013