GaN based semiconductor device
A semiconductor device according to an embodiment includes a first semiconductor layer of a first GaN based semiconductor, a second semiconductor layer of a second GaN based semiconductor having a band gap narrower than the first GaN based semiconductor, a third semiconductor layer of a third GaN based semiconductor having a band gap wider than the second GaN based semiconductor, a fourth semiconductor layer of a fourth GaN based semiconductor having a band gap narrower than the third GaN based semiconductor, a fifth semiconductor layer of a fifth GaN based semiconductor having a band gap wider than the fourth GaN based semiconductor, a gate dielectric provided directly on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, a gate electrode provided on the gate dielectric, a source and drain electrodes provided above the fifth semiconductor layer.
1. A semiconductor device comprising:
a first semiconductor layer of a first GaN based semiconductor;
a second semiconductor layer of a second GaN based semiconductor provided above the first semiconductor layer, the second GaN based semiconductor having a band gap narrower than that of the first GaN based semiconductor;
a third semiconductor layer of a third GaN based semiconductor provided above the second semiconductor layer, the third GaN based semiconductor having a band gap wider than that of the second GaN based semiconductor;
a fourth semiconductor layer of a fourth GaN based semiconductor provided above the third semiconductor layer, the fourth GaN based semiconductor having a band gap narrower than that of the third GaN based semiconductor;
a fifth semiconductor layer of a fifth GaN based semiconductor provided above the fourth semiconductor layer, the fifth GaN based semiconductor having a band gap wider than that of the fourth GaN based semiconductor;
a gate dielectric provided directly on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer;
a gate electrode provided on the gate dielectric;
a source electrode provided above the fifth semiconductor layer; and
a drain electrode provided above the fifth semiconductor layer at the side opposite to the side of the gate electrode with respect to the source electrode.
2. The device according to claim 1 , wherein a thickness of the first semiconductor layer is larger than a thickness of the second semiconductor layer.
3. The device according to claim 1 , wherein a thickness of the second semiconductor layer is 300 nm or less.
4. The device according to claim 1 , wherein a thickness of the third semiconductor layer is 5 nm to 30 nm.
5. The device according to claim 1 , wherein the fifth semiconductor layer is n-type semiconductor.
6. The device according to claim 1 , wherein the first GaN based semiconductor has a composition represented by Al X1 In Y1 Ga 1-(X1+Y1) N (0≦X1≦1, 0≦Y1≦1, and 0≦X1+Y1<1), the second GaN based semiconductor has a composition represented by Al X2 In Y2 Ga 1-(X2+Y2) N (0≦X2≦1, 0≦Y2≦1, and 0≦X2+Y2<1), the third GaN based semiconductor has a composition represented by Al X3 In Y3 Ga 1-(X3+Y3) N (0≦X3≦1, 0≦Y3≦1, and 0≦X3+Y3<1), the fourth GaN based semiconductor has a composition represented by Al X4 In Y4 Ga 1-(X4+Y4) N (0≦X4≦1, 0≦Y4≦1, and 0≦X4+Y4<1), and the fifth GaN based semiconductor has a composition represented by Al X5 In Y5 Ga 1-(X5+Y5) N (0≦X5≦1, 0≦Y5≦1, and 0≦X5+Y5<1).
7. The device according to claim 6 , wherein X1+Y1, X2+Y2, X3+Y3, X4+Y4, and X5+Y5 satisfy relations of X1+Y1>X2+Y2, X3+Y3>X2+Y2, and X5+Y5>X4+Y4.
8. The device according to claim 6 , wherein X1, X3, and X5 satisfy a relation of X5>X3≧X1.
9. The device according to claim 6 , wherein Y3 and Y5 satisfy a relation of Y5>Y3.