IP Library Granted Patent US 9,195,579
Granted Patent B2
US 9,195,579 · App. 13/754,161 · Granted Nov 24, 2015

Page replacement method and memory system using the same

Inventors: Oh-Seong Kwon (Hwasung, KR); Hwansoo Han (Seoul, KR); Sun-Young Lim (Hwasung, KR); Seonggun Kim (Hwasung, KR)
Assignees: Samsung Electronics Co., Ltd.; Research & Business Foundation, Sungkyunkwan University
G06F12/0238G06F12/08G06F12/121G06F12/0246G06F2212/205G06F2212/222
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Quick Facts
Patent No.
US 9,195,579
App. No.
13/754,161
Granted
Nov 24, 2015
Kind
B2
Abstract

A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

Claims (19)

1. A memory system, comprising:

a central processing unit (CPU);

a nonvolatile flash memory electrically coupled in the memory system to communicate with said CPU; and

a main memory configured to swap an incoming code page read from a nonvolatile non-flash memory for a target code page therein, in response to a first command issued by said CPU;

wherein said main memory is configured to swap the target code page in said main memory to said nonvolatile flash memory in the event a page capacity of said main memory is at a threshold capacity; and

wherein said main memory includes a page table configured to maintain refault bit values therein, which indicate for each of a plurality of code pages stored in said main memory how many times the corresponding code pages have been discarded from said main memory without being written into said nonvolatile flash memory.

2. The memory system of claim 1 , wherein said CPU is configured to perform a frequency of use analysis on the target code page by accessing the page table to determine whether the target code page is to be swapped into said nonvolatile flash memory or discarded because the corresponding refault bit value indicates an insufficient number of prior discards associated with the target code page.

3. The memory system of claim 1 , wherein the nonvolatile non-flash memory is a disk drive storage device.

4. A memory system, comprising:

a CPU;

a nonvolatile memory configured to directly exchange data with the CPU; and

a main memory configured to store data loaded from a disk and the nonvolatile memory in response to operation of the CPU;

wherein the nonvolatile memory is used as a swap device of the main memory;

wherein the CPU swaps a code page selected as a replacing target to the nonvolatile memory from the main memory; and

wherein said main memory includes a page table configured to maintain refault bit values therein, which indicate for each of a plurality of code pages stored in said main memory how many times the corresponding code pages have been discarded from said main memory without being written into said nonvolatile memory.

5. The memory system of claim 4 , wherein the CPU selects a replacing target according to a Least Recently Used (LRU) policy.

6. A method of operating a memory system containing a volatile main memory, a nonvolatile flash memory and a nonvolatile disk drive memory therein, said method comprising:

swapping a first incoming code page read from the disk drive memory for a target code page within the main memory, in response to a first CPU command, said main memory containing a page table configured to maintain refault bit values therein, which indicate for each of a plurality of code pages stored in the main memory, including the target code page, how many times each corresponding code page has been discarded from the main memory without being written into the flash memory; and

swapping a second incoming code page read from the disk drive memory for the first incoming code page within the main memory, in response to a second CPU command, by evaluating a first refault bit value associated with the first incoming code page and then either: (i) discarding the first incoming code page from the main memory upon determining that the first refault bit value has a magnitude less than a predetermined threshold, or (ii) transferring the first incoming code page from the main memory to the flash memory upon determining that the first refault bit value has a magnitude at or greater than the predetermined threshold.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2013
From: KWON, OH-SEONG; LIM, SUN-YOUNG; KIM, SEONGGUN; HAN, HWANSOO
To: SAMSUNG ELECTRONICS CO., LTD.; RESEARCH & BUSINESS FOUNDATION, SUNGKYUNKWAN UNIVERSITY
Reel/Frame 029727/0722 →
Priority Claims (1)
KR 10-2012-0034429 · Apr 3, 2012 · national
Continuity (1)
Related Publication 20130262738A1 · Oct 3, 2013