Bonding transistor wafer to LED wafer to form active LED modules
LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer, containing an array of vertical MOSFETS, is aligned and bonded to an LED wafer, containing a corresponding array of vertical LEDs, and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display.
1. An integrated driver and light emitting diode (LED module comprising:
a vertical light emitting diode (LED) having a top LED conducting surface and a bottom LED conducting surface, the LED comprising at least an n-type epitaxial layer and a p-type epitaxial layer; and
a vertical transistor in series with the LED, the transistor and the LED having been formed separately and independently prior to being connected in series, the vertical transistor comprising at least an n-type silicon area and a p-type silicon area,
the transistor having a first terminal, a second terminal, and a third terminal, the first terminal being a bottom conducting surface of the transistor, the bottom conducting surface of the transistor being electrically and mechanically bonded to the top LED conducting surface,
the LED and transistor being substantially the same size,
the LED being configured to emit light when a first voltage is applied to the bottom LED conducting surface, a second voltage is applied to the second terminal, and a first control voltage is applied to the third terminal.
2. The module of claim 1 wherein the transistor has a top surface, wherein the second terminal and third terminal are formed on the top surface.
3. The module of claim 1 wherein the transistor is a FET.
4. The module of claim 3 wherein the first terminal is a drain terminal, the second terminal is a gate terminal, and the third terminal is a source terminal.
5. The module of claim 3 wherein the first terminal is a drain terminal, the second terminal is a source terminal, and the third terminal is a gate terminal.
6. The module of claim 1 wherein the transistor is a bipolar transistor.
7. The module of claim 1 wherein the top LED conducting surface is an anode and the bottom LED conducting surface is a cathode.
8. The module of claim 1 wherein the top LED conducting surface is a cathode and the bottom LED conducting surface is an anode.
9. The module of claim 1 wherein the LED is GaN-based and the transistor is silicon-based.
10. A method of forming a lighting device comprising:
forming a first array of vertical light emitting diodes (LEDs) in an LED wafer, each of the LEDs having a top LED conducting surface and a bottom LED conducting surface; and
forming a second array of vertical transistors in a transistor wafer, each of the transistors having a first terminal, a second terminal, and a third terminal, the first terminal being a bottom conducting surface of the transistors;
aligning the LED wafer with the transistor wafer such that each transistor area in the transistor wafer is aligned with each LED area in the LED wafer;
forming bonded wafers by bonding the top LED conducting surface of the LED wafer to the bottom conducting surface of the transistor wafer to electrically and mechanically bond the top LED conducting surface to the bottom conducting surface by a bonding layer; and
singulating the bonded wafers to create individual modules, each module containing at least a driver transistor and an LED.
11. The method of claim 10 wherein forming the first array of vertical LEDs comprises epitaxially growing LED layers over an LED growth substrate, the method further comprising removing the growth substrate after bonding the top LED conducting surface of the LED wafer to the bottom conducting surface of the transistor wafer.
12. The method of claim 10 wherein forming the second array of vertical transistors comprises forming transistor regions over a substrate, the method further comprising removing the substrate prior to bonding the top LED conducting surface of the LED wafer to the bottom conducing surface of the transistor wafer.
13. The method of claim 12 further comprising affixing a first carrier wafer to a top surface of the transistor wafer prior to removing the substrate.
14. The method of claim 13 further comprising affixing a second carrier wafer to the bottom LED conducting surface, and then removing the first carrier wafer to process a top surface of the transistor wafer.
15. The method of claim 14 further comprising etching trenches in the LED wafer and transistor wafer down to the second carrier wafer to define the individual modules, then removing the individual modules from the second carrier wafer.
16. The method of claim 14 further comprising packaging the individual modules to form an array of modules for generating light.
17. The method of claim 16 wherein the array of modules is part of an addressable color display.
18. The method of claim 16 wherein the array of modules is part of a light source generating white light.