High-voltage metal-oxide semiconductor transistor and method of fabricating the same
The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.
1. A method of fabricating a HVMOS transistor, comprising:
providing a substrate;
forming a patterned shielding layer, covered on the substrate;
performing an ion implantation by using the patterned shielding layer as a mask, to form a first doped region, and removing the patterned shielding layer;
performing a thermal process to form a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises a protruded portion and a recessed portion, the protruded portion is disposed at two sides of the recessed portion and comprises a thickness greater than a thickness of the recessed portion, and a border between the protruded portion and the recessed portion is vertically aligned with a side edge of the first doped region;
forming a gate electrode on the gate dielectric layer; and
forming a source and drain region embedded in the substrate at two sides of the gate electrode.
2. The method according to claim 1 , wherein a channel region is further defined in the substrate between the source and drain region, and the channel region corresponding to the recessed portion of the gate dielectric layer in a vertical direction.
3. The method according to claim 1 , wherein the step of performing the ion implantation comprises providing fluorine or oxygen and providing at least one of inert gas.
4. The method according to claim 1 , wherein the step of forming the gate electrode comprises:
forming a gate electrode layer on the gate dielectric layer; and
patterning the gate electrode layer and the gate dielectric layer to form the gate electrode.
5. The method according to claim 1 , wherein the step of forming the gate electrode comprises:
forming a gate electrode layer on the gate dielectric layer; and
patterning the gate electrode layer and using the gate dielectric layer as an etching stop layer, to form the gate electrode.
6. The method according to claim 1 , further comprising:
after the step of forming the gate electrode, performing an ion implantation by using the gate electrode as a mask to form a second doped region embedded in the substrate.
7. The method according to claim 1 , further comprising:
forming a spacer on a side wall of the gate electrode; and
performing an ion implantation by using the spacer and the gate electrode as a mask to form the source and drain region.