Random number generation using startup variances
Random numbers are generated according to a variety of solutions. A particular solution relates to a method for generating the random number. A common start signal is provided to each of a plurality of inverter components of a ring oscillator circuit. This causes the ring oscillator circuit to enter a metastable mode. At least a first bit and a second bit of a random number are both generated in parallel. The parallel generation of the bits involves the generation of the first bit from entropic properties of a signal of a first one of the plurality of inverter components and the generation of the second bit from entropic properties of a signal of a second one inverter components.
1. A method comprising:
providing a common start signal to each of a plurality of inverter components of a ring oscillator circuit and thereby causing the ring oscillator circuit to enter a metastable mode; and
generating, in parallel, at least a first bit and a second bit of a random number by generating the first bit from entropic properties of a signal of a first one of the plurality of inverter components; and
generating the second bit from entropic properties of a signal of a second one of the plurality of inverter components.
2. The method of claim 1 , wherein the step of generating a first bit includes latching a value from the first one of the plurality of inverter components in response to an enable signal that is asynchronous to the ring oscillator circuit.
3. The method of claim 1 , wherein the step of generating a first bit includes latching a value of a free-running counter in response to a transition of the signal of the first one of the plurality of inverter components.
4. The method of claim 1 , wherein the step of generating a first bit and the step of generating a second bit each include latching a value from a respective inverter component in response to an enable signal that is asynchronous to the ring oscillator circuit.
5. The method of claim 1 , wherein the step of generating a first bit includes quantification of the entropic properties of the signal of the first one of the plurality of inverter components in response to an enable signal having a rate that varies in a random manner.
6. The method of claim 1 , wherein the step of generating a first bit includes latching a value of a free-running counter in response to a transition of the signal of the first one of the plurality of inverter components and wherein the free-running counter is a non-sequential counter.
7. The method of claim 1 , further including implementing the steps of claim 1 for a second oscillator circuit to generate a second random number and comparing the two random numbers to detect correlations therebetween.
8. A random number generating circuit comprising:
at least three NAND gates connected in series to form a ring oscillator circuit;
a common startup signal line connected to an input of each of the least three NAND gates;
at least three entropic capture circuits, each entropic capture circuit configured and arranged to quantify, in parallel with the other entropic capture circuits, entropic properties of an output signal from a corresponding NAND gate; and
a memory storage circuit for concatenating and storing each of the quantified entropic properties as a respective bit of a random number.
9. The circuit of claim 8 , wherein the at least three entropic capture circuits include latches that receive the output of a respective NAND gate as an input and that are configured to latch the input in response to an enable signal.
10. The circuit of claim 8 , wherein the at least three entropic capture circuits include counters that receive the output of a respective NAND gate as an input and that are configured to store an output of the counters in response to an enable signal.
11. The circuit of claim 8 , wherein the at least three entropic capture circuits include free-running counters that are configured to store an output of the counters in response to a transition of a signal from an output of a respective NAND gate.
12. The circuit of claim 8 , further including multiple counters that are configured to operate in both sequential and non-sequential modes, wherein the counters are configured to generate a count value that is responsive to entropic properties of an output signal for a corresponding NAND gate.
13. The circuit of claim 12 , wherein the counters are configured to change between the modes in response to another entropic signal source.
14. The circuit of claim 8 , further including free-running counters configured and arranged to continuously count in a manner asynchronous to the NAND gates.
15. The circuit of claim 14 , wherein the at least three entropic capture circuits are configured and arranged to captured outputs of the free-running counters in response to transitions of the signals received from the NAND gates.
16. The circuit of claim 14 , wherein the free-running counters are configured and arranged to count by a value other than one.