CMOS interpolator for a serializer/deserializer communication application
A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.
1. A pulse amplified modulation (PAM) system comprising:
a phase-lock-loop (PLL) module configured to receive an input clock signal and provides a reference clock signal;
a phase interpolator (PI) module being configured to perform a digital to phase conversion, the PI module being coupled to the PLL module;
a delay-lock-loop (DLL) module configured to provide phase locking between data and DLL output clocks; and
a timing recovery loop module being configured to generate a driving signal for driving the PI module.
2. The system of claim 1 wherein the DLL module is configured to track a frequency offset.
3. The system of claim 1 wherein the timing recovery loop is coupled to the DLL module.
4. The system of claim 1 wherein the PLL comprises a frequency synthesizer.
5. The system of claim 1 wherein the timing recovery loop comprises a digital signal processor (DSP).