Bidirectional bipolar junction transistor operation, circuits, and systems with two base junctions clamped by default
Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
1. A switching circuit comprising:
a two-base bidirectional npn semiconductor switching device which includes both an n-type emitter/collector region and also a p-type base contact region on each of both first and second opposed surfaces of a p-type monolithic semiconductor die;
driving circuitry controlling said switching device, comprising
control circuitry which is connected separately to the base contact regions on the first and second opposed surfaces; and
first and second distinct voltage-limiting circuits, each comprising a series combination of a low-voltage diode and a normally-on switch, each voltage-limiting circuit connected to one of the first and second opposed surfaces so that, when the normally-on switch is on, the anode of the low-voltage diode is connected to the p-type base contact region, and the cathode of the low-voltage diode is connected to the n-type emitter/collector region;
wherein the low-voltage diode turns on at a forward voltage which is less than the diode drop of the p-n junction between an emitter/collector region and the semiconductor die;
whereby, while the normally-on switch is ON, the p-n junction between an emitter/collector region and the semiconductor die cannot ever operate under forward bias.
2. The switching circuit of claim 1 , wherein the normally-on switch is connected to the control circuitry.
3. The switching circuit of claim 1 , wherein the normally-on switch is a JFET.
4. The switching circuit of claim 1 , wherein the normally-on switch is a JFET having a gate connected to the control circuitry.
5. The switching circuit of claim 1 , wherein the die is silicon.
6. The switching circuit of claim 1 , wherein the low-voltage diode is a schottky barrier diode.
7. The switching circuit of claim 1 , wherein the die is silicon, and the low-voltage diode is a schottky barrier diode.
8. The switching circuit of claim 1 , wherein the emitter/collector region on the first surface is not directly electrically connected to the emitter/collector region on the second surface, except through the semiconductor die itself.
9. The switching circuit of claim 1 , wherein the base contact region on the first surface is not directly electrically connected to the base contact region on the second surface, except through the semiconductor die itself.
10. A switching circuit comprising:
a double-base bipolar transistor, having a distinct n-type emitter/collector region on each of both first and second opposite surfaces of a p-type semiconductor die, each emitter/collector region defining a p-n emitter junction with respect to the die;
first and second voltage-limiting circuits connected to said first and second opposite surfaces, wherein each said voltage-limiting circuit includes a diode and a normally-on switch in series, with the anode of the diode operatively connected to the p side of the respective emitter junction, and the cathode operatively connected to the n side of the respective emitter junction;
wherein the diodes in said voltage-limiting circuits have respective forward diode voltage drops which are substantially less than the forward diode voltage drop characteristic of the respective p-n emitter junction.
11. The switching circuit of claim 10 , wherein the normally-on switch is a JFET.
12. The switching circuit of claim 10 , wherein the die is silicon.
13. The switching circuit of claim 10 , wherein the diode is a schottky barrier diode.
14. The switching circuit of claim 10 , wherein the die is silicon, and the diode is a schottky barrier diode.
15. The switching circuit of claim 10 , wherein the emitter/collector region on the first surface is not directly electrically connected to the emitter/collector region on the second surface.
16. A switching circuit comprising:
a double-base bipolar transistor, having a distinct p-type emitter/collector region on each of both first and second opposite surfaces of an n-type semiconductor die, each emitter/collector region defining a p-n emitter junction with respect to the die;
first and second voltage-limiting circuits connected to said first and second surfaces, wherein each voltage-limiting circuit includes a diode and a normally-on switch in series, with the anode of the diode operatively connected to the p side of the respective emitter junction, and the cathode operatively connected to the n side of the respective emitter junction;
wherein the diodes in said voltage-limiting circuits have respective forward diode voltage drops which are substantially less than the forward diode voltage drop characteristic of the respective p-n emitter junction.
17. The switching circuit of claim 16 , wherein the normally-on switch is a JFET.
18. The switching circuit of claim 16 , wherein the die is silicon.
19. The switching circuit of claim 16 , wherein the diode is a schottky barrier diode.
20. The switching circuit of claim 16 , wherein the die is silicon, and the diode is a schottky barrier diode.