Compact and low loss Y-junction for submicron silicon waveguide
A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.
1. A 1×2 power splitter for use in submicron silicon waveguides, comprising:
an input port having a taper width W i , said input port configured to receive an optical signal having a power of substantially P watts; and
a pair of output ports having respective taper widths W o1 and W o2 and spaced apart by a distance D, said pair of output ports configured to provide substantially equal output signals each having a power of substantially P/2 Watts;
said 1×2 power splitter having a width greater than W o1 +W o2 +D at a location intermediate between said input port and said output ports and a footprint of no larger than 1.4 μm×2 μm in area.
2. The 1×2 power splitter for use in submicron silicon waveguides of claim 1 , wherein said input port has a taper width of 0.5 μm.
3. The 1×2 power splitter for use in submicron silicon waveguides of claim 1 , wherein at least one of said output ports has a taper width of 0.5 μm.
4. The 1×2 power splitter for use in submicron silicon waveguides of claim 1 , wherein said 1×2 power splitter has a total output width of 1.2 μm.
5. The 1×2 power splitter for use in submicron silicon waveguides of claim 1 , wherein said 1×2 power splitter has a minimum feature size of 200 nm.
6. The 1×2 power splitter for use in submicron silicon waveguides of claim 1 , wherein said 1×2 power splitter is configured to be manufactured using a CMOS fabrication process.
7. The 1×2 power splitter for use in submicron silicon waveguides of claim 6 , wherein said CMOS fabrication process is a process conducted using a 248 nm stepper.
8. The 1×2 power splitter for use in submicron silicon waveguides of claim 6 , wherein said CMOS fabrication process is a process conducted using a 193 nm stepper.