IP Library Granted Patent US 9,218,575
Granted Patent B2
US 9,218,575 · App. 14/018,217 · Granted Dec 22, 2015

Periodic training for unmatched signal receiver

Inventors: Christopher P. Mozak (Beaverton, OR); James A. McCall (Portland, OR)
Assignee: Intel Corporation
G06N99/005G05B13/02
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Quick Facts
Patent No.
US 9,218,575
App. No.
14/018,217
Granted
Dec 22, 2015
Kind
B2
Abstract

I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.

Claims (48)

1. A method comprising:

entering, by a memory device, a training mode of the memory device;

receiving a training signal from a controller while in the training mode, the training signal including a data stream;

sampling the data stream of the training signal with sampling circuitry;

tracking, by the memory device, a number of data errors in the sampling of the data stream of the training signal; and

causing an adjustment to at least one input/output (I/O) parameter based on the number of data errors.

2. The method of claim 1 , wherein entering the training mode comprises entering the training mode during a refresh mode of the memory device.

3. The method of claim 1 , wherein receiving the training signal comprises:

receiving the training signal as a write command; and

discarding the training signal instead of writing it to a memory array of the memory device.

4. The method of claim 1 , wherein tracking the number of errors comprises:

counting with a counter a number of errors that occur over a sequence of training signals.

5. The method of claim 3 , wherein causing the adjustment comprises:

sending the number of errors to the controller to cause the controller to determine the at least one I/O parameter to adjust.

6. The method of claim 1 , wherein causing the adjustment comprises:

causing the adjustment to a receive I/O parameter of the memory device.

7. The method of claim 1 , wherein causing the adjustment comprises:

causing the adjustment to a transmit I/O parameter of the controller.

8. The method of claim 1 , wherein causing the adjustment further comprises:

computing a search function to determine the at least one I/O parameter to adjust.

9. A memory device comprising:

a state controller to cause the memory device to enter a training mode of the memory device;

a hardware contact to interface with a controller device, to receive a training signal from the controller while in the training mode, the training signal including a data stream;

receiver hardware to sample the data stream of the training signal and track a number of data errors in the sampling of the data stream of the training signal; and

logic to cause an adjustment to at least one input/output (I/O) parameter based on the number of data errors.

10. The memory device of claim 9 , wherein the state controller is to cause the memory device to enter the training mode during a refresh mode of the memory device.

11. The memory device of claim 9 , wherein the receiver hardware is to discard the training signal instead of writing it to a memory array of the memory device.

12. The memory device of claim 9 , further comprising:

a counter to count a number of errors that occur over a sequence of training signals.

13. The memory device of claim 9 , wherein the logic is to cause an adjustment to at least one I/O parameter of a transmitter of the controller.

14. The memory device of claim 9 , wherein the logic further comprises:

search function logic to determine the at least one I/O parameter to adjust.

15. A method comprising:

sending a training signal as a write command to a memory device, where the memory device writes the training signal to a register but not to a memory array of the memory device, the training signal including a plurality of data values;

reading the training signal from the register;

checking the read training signal for errors in the plurality of data values; and

causing an adjustment to an input/output (I/O) parameter of the memory device based on a number of errors in the plurality of data errors.

16. The method of claim 15 , wherein causing the adjustment comprises:

causing the adjustment to a transmit I/O parameter of the controller.

17. The method of claim 15 , wherein causing the adjustment further comprises:

computing a search function to determine the at least one I/O parameter to adjust.

18. The method of claim 15 , further comprising:

sending a command to cause the memory device to enter a training state while in the refresh state.

19. A controller device comprising:

a hardware contact to interface with a memory device, the controller device, via the hardware contact, to send a training signal as a write command to the memory device in a refresh state, the training signal including a plurality of data values, where the memory device is to write the training signal including the plurality of data values to a register but not to a memory array of the memory device; and

read the training signal including the plurality of data values from the register; and

logic to check the read training signal for errors in the plurality of data values and cause an adjustment to at least one input/output (I/O) parameter of the memory device based on a number of errors in the plurality of data values.

20. The controller device of claim 19 , wherein the logic is to cause an adjustment to at least one I/O parameter of the controller.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2014
From: MOZAK, CHRISTOPHER P.; MCCALL, JAMES A.
To: INTEL CORPORATION
Reel/Frame 032619/0773 →
Continuity (1)
Related Publication 20150066819A1 · Mar 5, 2015