IP Library Granted Patent US 9,221,676
Granted Patent B2
US 9,221,676 · App. 14/590,839 · Granted Dec 29, 2015

Internal electrical contact for enclosed MEMS devices

Inventors: Kegang Huang (Fremont, CA); Jongwoo Shin (Pleasanton, CA); Martin Lim (San Mateo, CA); Michael Julian Daneman (Campbell, CA); Joseph Seeger (Menlo Park, CA)
Assignee: INVENSENSE, INC.
B81C1/00301
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Quick Facts
Patent No.
US 9,221,676
App. No.
14/590,839
Granted
Dec 29, 2015
Kind
B2
Abstract

A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

Claims (19)

1. A MEMS device comprising:

a MEMS substrate, the MEMS substrate includes a first semiconductor layer, a second semiconductor layer and a dielectric layer in between, the first semiconductor layer has a first and second surfaces, wherein the first surface is in contact with the dielectric layer;

wherein MEMS structures are formed from the second semiconductor layer and

includes a plurality of first conductive pads;

a base substrate which includes a plurality of second conductive pads thereon; wherein the second conductive pads are connected to the first conductive pads; and

a conductive connector formed through only the dielectric layer, the second semiconductor layer and the first surface of the first semiconductor layer to provide electrical coupling between the first semiconductor layer and the second semiconductor layer, whereby the base substrate is electrically connected to the second semiconductor layer and the first semiconductor layer.

2. The MEMS device of claim 1 , wherein the plurality of first conductive pads comprise germanium.

3. The MEMS device of claim 1 , wherein the plurality of second conductive pads comprise aluminum.

4. The MEMS device of claim 1 , wherein the MEMS substrate includes one or more etched vias filled by conductive material to form the conductive connector.

5. The MEMS device of claim 1 further comprising a seal ring, the seal ring comprising a continuous ring to form an enclosure surrounding the MEMS structures and formed by a connection of one of the first conductive pads and one of the second conductive pads.

6. The MEMS device of claim 5 , wherein the first conductive pad is electrically connected to the first semiconductor layer.

7. The MEMS device of claim 5 , wherein the conductive connector is positioned in the enclosure of the seal ring, or wherein the conductive connector is positioned outside the enclosure of the seal ring.

8. The MEMS device of claim 5 , wherein the conductive connector is positioned within the seal ring.

9. The MEMS device of claim 1 , wherein the connection between the first conductive pad and second conductive pad is a eutectic bond.

10. The MEMS device of claim 1 , wherein the MEMS structures are electrically isolated from the first semiconductor layer.

11. The MEMS device of claim 4 , wherein the conductive material filling the one or more vias comprises any of polysilicon, germanium, and tungsten, or wherein the conductive material filling the one or more vias comprises any of aluminum, titanium, and titanium nitride.

12. The MEMS device of claim 5 , wherein the seal ring provides a hermetic seal.

13. The MEMS device of claim 1 , wherein surface of the first semiconductor layer facing the second semiconductor layer includes cavities therein.

14. The MEMS device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise any of single crystal silicon materials or polysilicon materials.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2015
From: HUANG, KEGANG; SHIN, JONGWOO; LIM, MARTIN; DANEMAN, MICHAEL J.; SEEGER, JOSEPH
To: INVENSENSE, INC.
Reel/Frame 034648/0053 →
Continuity (4)
Continuation 14456973 · Aug 11, 2014
Continuation 14033366 · Sep 20, 2013
Division 13754462 · Jan 30, 2013
Related Publication 20150336792A1 · Nov 26, 2015