Semiconductor apparatus capable of detecting whether pad and bump are stacked
A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.
1. A semiconductor apparatus comprising a semiconductor chip including:
a second pad including a first metal layer coupled to a first pad and a second metal layer coupled to a through-via;
a bump stacked on the first and second metal layers; and
a path detour unit configured to electrically couple the first and second metal layers in response to a control signal,
wherein the first and second metal layers are electrically isolated from each other.
2. The semiconductor apparatus of claim 1 , wherein the control signal is generated when the bump does not have contact with at least one of the first and second metal layers.
3. The semiconductor apparatus of claim 1 , wherein the first pad receives a signal from outside the semiconductor apparatus.
4. The semiconductor apparatus of claim 1 , wherein the second pad is configured to receive a signal from a controller chip through the bump.
5. A semiconductor apparatus comprising a semiconductor chip including:
a second pad including a first metal layer coupled to a first pad and a second metal layer coupled to a through-via;
a bump stacked on the first and second metal layers; and
a path detour unit configured to bypass the second pad and electrically couple the first pad to the through-via in response to a control signal
wherein the first and second metal layers are electrically isolated from each other.
6. A semiconductor apparatus comprising a semiconductor chip including:
a direct access pad configured to receive data from external to the semiconductor apparatus;
an interface pad including first and second metal layers, which are electrically isolated from each other, and over which a bump is stacked;
a write unit electrically coupled to the second metal layer, and configured to transmit data, which is received from the second metal layer, to a through-via; and
a read unit configured to transmit data, which is received from the through-via, to the direct access pad.
7. The semiconductor apparatus of claim 6 , wherein the semiconductor chip further includes a path detour unit configured to electrically couple the first and second metal layers in response to a control signal.
8. The semiconductor apparatus of claim 7 , wherein the control signal is generated when the bump does not have contact with at least one of the first and second metal layers.
9. The semiconductor apparatus of claim 6 , wherein the semiconductor apparatus further includes a path detour unit configured to electrically couple the direct access pad to the through-via in response to a control signal.
10. The semiconductor apparatus of claim 6 , wherein the through-via provides an electrical connection to another semiconductor chip.
11. The semiconductor apparatus of claim 6 , wherein the semiconductor chip is configured to receive data from a controller chip through the bump and the interface pad.