IP Library Granted Patent US 9,224,745
Granted Patent B2
US 9,224,745 · App. 13/668,815 · Granted Dec 29, 2015

Method of manufacturing semiconductor device

Inventor: Satoshi Torii (Kuwana, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H01L27/11546H01L21/28273H01L28/40H01L29/66825
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Quick Facts
Patent No.
US 9,224,745
App. No.
13/668,815
Granted
Dec 29, 2015
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask.

Claims (52)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a conductive film in a memory region and a logic region of a semiconductor substrate;

forming a first gate electrode in the memory region by patterning the conductive film in the memory region while leaving the conductive film in the logic region;

after forming the first gate electrode, forming a mask film above the conductive film left in the logic region, and above the first gate electrode;

removing the mask film in the logic region;

after removing the mask film in the logic region, forming a first resist film above the mask film left in the memory region, and above the conductive film left in the logic region;

forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask;

removing the first resist film; and

removing the mask film,

wherein, in the forming the mask film, the mask film is formed on a lateral surface of the first gate electrode and a top surface of the first gate electrode, and,

in the forming the second gate electrode in the logic region, the second gate electrode is formed in the logic region while leaving the mask film on the lateral surface of the first gate electrode and the top surface of the first gate electrode in the memory region.

2. The method of manufacturing a semiconductor device according to claim 1 , the method further comprising:

before forming the mask film, forming a side wall insulating film at each side of the first gate electrode wherein:

in the forming the mask film, the mask film is also formed on the side wall insulating films; and

in the removing the mask film, the mask film is removed by etching under an etching condition that makes the mask film have a higher etching rate than the side wall insulating films.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein:

in the forming the side wall insulating film, a silicon nitride film is formed as the side wall insulating film;

in the forming the mask film, a silicon oxide film is formed as the mask film; and

in the removing the mask film, the mask film is removed by wet etching using hydrofluoric acid.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein in the forming the mask film, the mask film is formed with such a thickness that the mask film remains above the first gate electrode at the time point when the second gate electrode is formed.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein in the forming the mask film, an insulating film having a higher etching rate than a silicon thermal oxide film is formed as the mask film.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein a silicon oxide film is formed as the insulating film by CVD using TEOS gas.

7. The method of manufacturing a semiconductor device according to claim 5 , the method further comprising:

before the forming the mask film, forming the silicon thermal oxide film on a lateral surface of the first gate electrode and on the semiconductor substrate at each side of the first gate electrode, wherein

the forming the mask film is performed in a state where the silicon thermal oxide film is formed.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein the removing the mask film in the logic region further comprises:

forming a second resist film on the mask film; and

removing the mask film in the logic region by wet etching using the second resist film as a mask.

9. The method of manufacturing a semiconductor device according to claim 1 , the method further comprising:

after the removing the mask film, forming a metal silicide film on a surface of the semiconductor substrate besides each of the first gate electrode and the second gate electrode.

10. The method of manufacturing a semiconductor device according to claim 1 , the method further comprising:

before the forming the conductive film, forming an underlying conductive film in the memory region of the semiconductor substrate; and

forming an intermediate insulating film on the underlying conductive film, wherein:

in the forming the conductive film, the conductive film is formed on the intermediate insulating film; and

in the forming the first gate electrode, a control gate of a flash memory cell is formed as the first gate electrode, and a floating gate of the flash memory cell is formed out of the underlying conductive film under the first gate electrode by patterning the intermediate insulating film and the underlying conductive film while leaving the intermediate insulating film under the first gate electrode.

11. The method of manufacturing a semiconductor device according to claim 10 , wherein:

the logic region includes a first logic region and a second logic region;

in the forming the underlying conductive film, the underlying conductive film is formed in the logic region of the semiconductor substrate;

in the forming the first gate electrode, the underlying conductive film in the first logic region is patterned to form a first conductive pattern, as well as the conductive film in the first logic region is patterned to form a second conductive pattern;

in the removing the mask film in the logic region, the mask film in the second logic region is removed, while a first opening including a partial region of the first conductive pattern inside thereof is exposed is formed in the mask film in the first logic region;

in the forming the first resist film, a window overlapping with the first opening is formed in the first resist film in the first logic region; and

in the forming the second gate electrode, the second conductive pattern is etched through the window to form a second opening in the second conductive pattern, as well as to form the second gate electrode out of the conductive film in the second logic region, the method further comprising:

removing the intermediate insulating film in the partial region of the first conductive pattern;

forming an interlayer insulating film in the memory region and the logic region of the semiconductor substrate;

forming a hole in the interlayer insulating film inside each of the first opening and the second opening; and

forming in the hole a conductive plug electrically connected to the partial region in the first conductive pattern.

12. The method of manufacturing a semiconductor device according to claim 11 , wherein a diameter of the window is larger than a diameter of the first opening.

13. The method of manufacturing a semiconductor device according to claim 11 , wherein a capacitor is formed by the first conductive pattern, the intermediate insulating film, and the second conductive pattern.

14. The method of manufacturing a semiconductor device according to claim 11 , wherein the first conductive pattern is a resistor of a resistive element.

15. The method of manufacturing a semiconductor device according to claim 11 , wherein in the forming the first gate electrode, the underlying conductive film in the logic region is patterned to form a third gate electrode as a portion of the first conductive pattern.

16. The method of manufacturing a semiconductor device according to claim 1 , wherein in the forming the mask film, the mask film is formed in contact with the top surface of the first gate electrode.

17. The method of manufacturing a semiconductor device according to claim 1 , wherein a top surface of the conductive film left in the logic region is flat at the time point when the first resist film is formed.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2012
From: TORII, SATOSHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 029264/0075 →
Priority Claims (1)
JP 2011-289254 · Dec 28, 2011 · national
Continuity (1)
Related Publication 20130171814A1 · Jul 4, 2013