Method for wear leveling in a nonvolatile memory

1. A system, comprising:

a program memory;

a processor communicatively coupled to the program memory; and

at least one nonvolatile memory, communicatively coupled to the processor, comprising electrically erasable and programmable memory cells, wherein the program memory stores instructions which, when executed by the processor, cause the processor to:

define data pages in a first nonvolatile memory zone;

define in the data pages programmable data blocks;

define in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone wherein each of the data pages is associated with a metadata structure of the metadata pages and each metadata structure includes a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attribute to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased; and

arrange wear counters attributed to metadata pages inside respective metadata pages.

2. The system of claim 1 wherein the instructions cause the processor to, before erasing a metadata page:

write in the second nonvolatile memory zone a temporary information structure comprising: an address in the second nonvolatile memory zone of the metadata page and a wear counter attributed to the metadata page.

3. The system of claim 1 wherein instructions cause the processor to, after having erased a metadata page:

read a wear counter attributed to the metadata page from a temporary information structure including an address in the second nonvolatile memory zone of the metadata page and the wear counter attributed to the metadata page;

increment the wear counter read from the temporary information structure; and

write the incremented wear counter in the erased metadata page.

4. The system of claim 1 wherein the instructions cause the processor to:

write, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erase data pages having a status of invalid as indicated in an associated metadata structure of the data page.

5. The system of claim 1 wherein the instructions cause the processor to:

invalidate a metadata structure associated with an erased data page;

attribute a new metadata structure to the erased data page; and

write in the new metadata structure an incremented value of a wear counter present in the invalidated metadata structure.

6. The system of claim 1 wherein the instructions cause the processor to:

in response to a read command of other data having a logical address:

find, in the second nonvolatile memory zone, a metadata structure containing the logical address and associated with valid data;

read, in the metadata structure found, an address of the other data in the first memory zone; and

read the other data in the first nonvolatile memory zone.

7. The system of claim 1 wherein the instructions cause the processor to:

before writing, in the second nonvolatile memory zone, the address of a metadata page, write in the temporary information structure a start flag, and

after having erased a wear counter attributed to the metadata page, write a final flag in the temporary information structure.

8. The system of claim 1 , comprising a volatile memory to store a look-up-table, wherein the instructions cause the processor to, at a system start-up:

read the metadata pages stored in the second non-volatile memory zone; and

construct the look-up table based on the reading of the metadata pages.

9. The system of claim 1 , comprising an integrated circuit including at least one of the program memory; the processor; and the at least one nonvolatile memory.

10. A non-transitory computer-readable medium containing contents which cause one or more processing devices to perform a method, the method comprising:

defining data pages in a first nonvolatile memory zone;

defining in the data pages programmable data blocks;

defining in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone, wherein each of the data pages is associated with a metadata structure of the metadata pages and each metadata structure includes a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attributing to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased; and

arranging a wear counter attributed to a metadata page inside the metadata page.

11. The medium of claim 10 wherein the method comprises:

before erasing the metadata page, writing in the second nonvolatile memory zone a temporary information structure comprising: an address in the second nonvolatile memory zone of the metadata page and the wear counter attributed to the metadata page.

12. The medium of claim 10 wherein the method comprises:

after erasing the metadata page:

reading a wear counter attributed to the metadata page from a temporary information structure, the temporary information structure including an address in the second nonvolatile memory zone of the metadata page and a wear counter of the metadata page;

incrementing the wear counter read from the temporary information structure; and

writing the incremented wear counter in the erased metadata page.

13. The medium of claim 10 wherein the method comprises:

writing, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erasing data pages having a status of invalid as indicated in an associated metadata structure of the data page.

14. The medium of claim 10 wherein the method comprises:

invalidating a metadata structure associated with an erased data page;

attributing a new metadata structure to the erased data page; and

writing in the new metadata structure an incremented value of a wear counter present in the invalidated metadata structure.

15. A system, comprising:

at least one nonvolatile memory including electrically erasable and programmable memory cells; and

a hard-wired sequencer coupled to the at least one nonvolatile memory and configured to:

define data pages in a first nonvolatile memory zone;

define in the data pages programmable data blocks;

define in a second nonvolatile memory zone, metadata pages comprising metadata structures associated with the data pages present in the first nonvolatile memory zone, wherein each of the data pages is associated with a metadata structure of the metadata pages and each metadata structure includes a wear counter containing a value representative of a number of times that the data page associated with the metadata structure has been erased;

attribute to each metadata page a wear counter containing a value representative of a number of times that a metadata page to which the wear counter is attributed has been erased; and

arrange a wear counter attributed to a metadata page inside the metadata page.

16. The system of claim 15 wherein the hard-wired sequencer is configured to:

before erasing the metadata page, write in the second nonvolatile memory zone a temporary information structure comprising: an address in the second nonvolatile memory zone of the metadata page and the wear counter attributed to the metadata page.

17. The system of claim 15 wherein the hard-wired sequencer is configured to:

after erasing the metadata page:

read a wear counter attributed to the metadata page from a temporary information structure, the temporary information structure including an address in the second nonvolatile memory zone of the metadata page and a wear counter of the metadata page;

increment the wear counter read from the temporary information structure; and

write the incremented wear counter in the erased metadata page.

18. The system of claim 15 wherein the hard-wired sequencer is configured to:

write, in each metadata structure associated with a data page, an information about a status, valid or invalid, of the data page; and

erase data pages having a status of invalid as indicated in an associated metadata structure of the data page.

19. The system of claim 15 wherein the hard-wired sequencer comprises a state machine.