Method for manufacturing a fin MOS transistor
A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.
1. A method for manufacturing a fin MOS transistor from an SOI-type structure comprising a semiconductor layer on a silicon oxide layer coating a support made of a semiconductor material, this method comprising the steps of:
a) forming, from a surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way through the silicon oxide layer to reach a top surface of the support made of the semiconductor material;
b) etching sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin;
c) filling said at least one recess with a material selectively etchable over silicon oxide; and
d) continuing said at least one trench delimiting the at least one fin all the way to an intermediate level of the support made of the semiconductor material.
2. The method of claim 1 , wherein said material selectively etchable over silicon oxide has a greater dielectric constant than silicon oxide.
3. The method of claim 1 , wherein said material selectively etchable over silicon oxide is a nitride.
4. The method of claim 1 , further comprising the step of coating with a nitride layer sides, accessible from said at least one trench, of a portion of the support made of the semiconductor material located under the fin.
5. The method of claim 4 , further comprising, before said coating step, a step of forming, from said at least one trench, a recess in the portion of the support made of the semiconductor material located under the fin.
6. The method of claim 4 , further comprising, before said coating step, a step of deposition of a silicon oxide layer on said sides of the portion of the support made of the semiconductor material located under the fin.
7. The method of claim 1 , further comprising the step of filling the continuation of said at least one trench with silicon oxide.
8. The method of claim 1 , further comprising a step during which sides and an upper surface of the fin are exposed.
9. The method of claim 1 , further comprising the step of forming a gate stack coating the sides and the upper surface of the fin.
10. A method for manufacturing a fin MOS transistor from an SOI-type structure comprising a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method comprising the steps of:
removing first portions of the semiconductor layer and silicon oxide layer to define a trench on each side of a fin which include a second portion of the semiconductor layer and a second portion of the silicon oxide layer;
wherein removing comprises etching completely through the first portion of the silicon oxide layer to reach a semiconductor surface of the semiconductor support;
laterally etching the sides of the second portion of the silicon oxide layer located under the second portion of the semiconductor layer for the fin to form a lateral recess on each side of the etched second portion of the silicon oxide layer underneath the second portion of the semiconductor layer for the fin;
filling said lateral recess on each side of the etched second portion of the silicon oxide layer with a material selectively etchable over silicon oxide; and
extending the trench on each side of the fin from the semiconductor surface into an upper portion of said semiconductor support so as to form a semiconductor portion made from the semiconductor support underneath said fin.
11. The method of claim 10 , further including the step of coating sides of the second portion of the semiconductor layer for the fin with an oxide layer.
12. The method of claim 10 , wherein the step of extending comprises performing an isotropic etch on the upper portion of said semiconductor support, said oxide layer coating sides of the second portion of the semiconductor layer for the fin functioning to protect the second portion of the semiconductor layer from said isotropic etch.
13. The method of claim 10 , further comprising the step of coating sides of the semiconductor portion with a nitride layer.
14. The method of claim 10 , further comprising the step of filling the extension of said trench with an oxide material that surrounds said fin.
15. The method of claim 14 , further comprising the steps of removing an upper portion of the oxide material which fills the extended trench and removing the oxide coating on sides of the second portion of the semiconductor layer for the fin so as to expose the second portion of the semiconductor layer for the fin.
16. The method of claim 15 , further comprising the step of covering the exposed second portion of the semiconductor layer for the fin with a gate stack layer.
17. A method for manufacturing a fin MOS transistor from an SOI-type structure comprising a first semiconductor layer on a silicon oxide layer coating a second semiconductor layer, this method comprising the steps of:
a) forming, from a surface of the first semiconductor layer, at least one trench delimiting at least one fin in the first semiconductor layer and extending all the way through the silicon oxide layer to reach a top surface of the second semiconductor layer;
b) etching sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin;
c) filling said at least one recess with a material selectively etchable over silicon oxide; and
d) continuing said at least one trench delimiting the at least one fin all the way to an intermediate level of the second semiconductor layer.
18. The method of claim 17 , wherein said material selectively etchable over silicon oxide has a greater dielectric constant than silicon oxide.
19. The method of claim 17 , wherein said material selectively etchable over silicon oxide is a nitride.
20. The method of claim 17 , further comprising the step of coating with a nitride layer the sides, accessible from said at least one trench, of a portion of the second semiconductor layer located under the fin.
21. The method of claim 20 , further comprising, before said coating step, a step of forming, from said at least one trench, a recess in the portion of the second semiconductor layer located under the fin.
22. The method of claim 20 , further comprising, before said coating step, a step of deposition of a silicon oxide layer on said sides of the portion of the second semiconductor layer located under the fin.
23. The method of claim 17 , further comprising the step of filling the continuation of said at least one trench with silicon oxide.
24. The method of claim 17 , further comprising a step during which sides and an upper surface of the fin are exposed.
25. The method of claim 17 , further comprising the step of forming a gate stack coating the sides and the upper surface of the fin.