Memory test sequencer
An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.
1. An interface device for a memory module comprising a plurality of DRAMs comprising:
a memory configured to store DRAM test program instructions; and
a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions;
wherein the programmable processing device is programmed to output a DRAM instruction by the DRAM test program instruction, wherein the DRAM instruction is selected from a group consisting of: read, write, recharge, refresh, and activate.
2. The interface device of claim 1 wherein the programmable processing device is programmed to perform one or more jump or loop operations specified by the DRAM test program instructions.
3. The interface device of claim 1 wherein the programmable processing device is programmed to perform one or more operations upon data stored within a register by the DRAM test program instructions.
4. The interface device of claim 1 wherein the programmable processing device is programmed to determine one or more DRAM memory addresses by the DRAM test program instructions.
5. The interface device of claim 1 wherein the programmable processing device is programmed to test one or more DRAM memory cells from the plurality of DRAMs by the DRAM test program instructions.
6. The interface device of claim 1 wherein the programmable processing device is programmed to write patterns of data to selected DRAMs from the plurality of DRAMs by the DRAM test program instructions.
7. The interface device of claim 1 wherein the programmable processing device is programmed to determining timing performance of selected DRAMs from the plurality of DRAMs by the DRAM test program instructions.
8. The interface device of claim 1 further comprising a bad cell repair module configured to store addresses of bad cells from the plurality of DRAMs.
9. An interface device for a memory module comprising a plurality of DRAMs comprising:
a memory configured to store DRAM test program instructions; and
a programmable processing device couple to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions;
wherein the programmable processing device comprises a superscalar processor.
10. The interface device of claim 9 wherein the programmable processing device is programmed to perform one or more jump or loop operations specified by the DRAM test program instructions.
11. The interface device of claim 9 wherein the programmable processing device is programmed to perform one or more operations upon data stored within a register by the DRAM test program instructions.
12. The interface device of claim 9 wherein the programmable processing device is programmed to determine one or more DRAM memory addresses by the DRAM test program instructions.
13. The interface device of claim 9 wherein the programmable processing device is programmed to test one or more DRAM memory cells from the plurality of DRAMs by the DRAM test program instructions.
14. The interface device of claim 9 wherein the programmable processing device is programmed to write patterns of data to selected DRAMs from the plurality of DRAMs by the DRAM test program instructions.
15. The interface device of claim 9 wherein the programmable processing device is programmed to determining timing performance of selected DRAMs from the plurality of DRAMs by the DRAM test program instructions.
16. The interface device of claim 9 further comprising a bad cell repair module configured to store addresses of bad cells from the plurality of DRAMs.