Circuits for controlling display apparatus
A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.
1. A display apparatus, comprising:
an array of light modulators, each light modulator having a first actuator configured to drive the light modulator towards a first state and a second actuator configured to drive the light modulator into a second state; and
a control matrix including, for each light modulator, a circuit for controlling the light modulator, the circuit including a first shutter-state inverter configured to control the first actuator of the light modulator and a second shutter-state inverter configured to control the second actuator of the light modulator, wherein an output of the first shutter-state inverter is electrically connected to only one input of the second shutter-state inverter and wherein the control matrix is configured to pre-bias a voltage at an output of the second shutter-state inverter and an input of the first shutter-state inverter.
2. The display apparatus of claim 1 , wherein the first shutter-state inverter includes a first charge transistor and a first discharge transistor and the second shutter-state inverter includes a second charge transistor and a second discharge transistor.
3. The display apparatus of claim 2 , wherein the first and second charge transistors are p-type transistors, and wherein the source of the first and second charge transistors are connected to an actuation voltage interconnect.
4. The display apparatus of claim 3 , wherein the first and second discharge transistors are n-type transistors, and wherein the source of the first and second discharge transistors are connected to the global update interconnect.
5. The display apparatus of claim 2 , further comprising a data store capacitor coupled to a gate of the second discharge transistor.
6. The display apparatus of claim 1 , wherein the circuit is configured to pre-bias a voltage at the output of the second shutter-state inverter and the input of the first shutter-state inverter prior to actuation of the light modulator by electrically connecting the output of the second shutter-state inverter and the input of the first shutter-state inverter to a biasing voltage source.
7. The display apparatus of claim 6 , wherein the first shutter-state inverter includes a first charge transistor and a first discharge transistor and the second shutter-state inverter includes a second charge transistor and a second discharge transistor, and wherein a drain of the second charge transistor and respective gates of the first charge transistor and the first discharge transistor are electrically connected to the biasing voltage source.
8. The display apparatus of claim 6 , wherein the biasing voltage source is electrically connected to the second shutter-state inverter and gates of the first shutter-state inverter via a capacitor.
9. The display apparatus of claim 6 , wherein the biasing voltage source is electrically connected to the second shutter-state inverter and gates of the first shutter-state inverter via a transistor.
10. The display apparatus of claim 1 , further comprising a data store capacitor coupled to the second shutter-state inverter and coupled to a first shutter state inverter via a data inverter.
11. The display apparatus of claim 1 , further comprising a first cascode transistor coupled to the first shutter-state inverter and a second cascode transistor coupled to the second shutter-state inverter.