SRAM write driver with improved drive strength
A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.
1. A subsystem configured to perform write operations with memory cells, the subsystem comprising:
a first bit line driver configured to write a data bit to a memory cell and including:
a first circuit element that is gated by a first write select line and coupled to a first data line configured to transport the data bit,
a second circuit element coupled to the first circuit element and gated by the first write select line, and
a third circuit element that is coupled to the memory cell and gated by the first circuit element and the second circuit element and is configured to output the data bit to the memory cell upon activation of the first data line and the first write select line.
2. The subsystem of claim 1 , wherein the first circuit element comprises a P-channel field effect transistor, and the second circuit element and the third circuit element comprise N-channel field effect transistors.
3. The subsystem of claim 1 , further comprising:
a second bit line driver configured to write the inverse of the data bit to the memory cell and including:
a fourth circuit element that is gated by the first write select line and coupled to a second data line configured to transport the inverse of the data bit,
a fifth circuit element coupled to the fourth circuit element and gated by the first write select line, and
a sixth circuit element coupled to the memory cell and gated by the fourth circuit element and the fifth circuit element and is configured to output the inverse of the data bit to the memory cell upon activation of the second data line and the first write select line.
4. The subsystem of claim 3 , wherein the fourth circuit element comprises a P-channel field effect transistor, and the fifth circuit element and the sixth circuit element comprise N-channel field effect transistors.
5. The subsystem of claim 3 , wherein the first bit line driver further includes a seventh circuit element coupled to the third circuit element and gated by the second data line.
6. The subsystem of claim 5 , wherein, in response to the second write data line being activated, the seventh circuit element is configured to pull the gate of the third circuit element to ground.
7. The subsystem of claim 6 , wherein the seventh circuit element comprises an N-channel field effect transistor.
8. The subsystem of claim 3 , wherein the second bit line driver further includes an eighth circuit element coupled to the sixth circuit element and gated by the first data line.
9. The subsystem of claim 8 , wherein, in response to the first write data line being activated, the eighth circuit element is configured to pull the gate of the sixth circuit element to ground.
10. The subsystem of claim 9 , wherein the eighth circuit element comprises an N-channel field effect transistor.
11. A computer-implemented method for performing write operations with memory cells, the method comprising:
causing a first write select line to activate a first circuit element that is coupled to a first data line and configured to output a data bit that is transported by the first data line; and
causing the first write select line to activate a second circuit element that is coupled to the first circuit element and to a third circuit element,
wherein the third circuit element is gated by the first circuit element and the second circuit element and configured to output the data bit to the memory cell upon activation of the first data line and the first write select line.
12. The computer-implemented method of claim 11 , further comprising:
causing the first write select line to activate a fourth circuit element that is coupled to a second data line and configured to output the inverse of the data bit that is transported by the second data line; and
causing the first write select line to activate a fifth circuit element that is coupled to the fourth circuit element and to a sixth circuit element,
wherein the sixth circuit element is gated by the fourth circuit element and the fifth circuit element and configured to output the inverse of the data bit to the memory cell upon activation of the second data line and the first write select line.
13. The computer-implemented method of claim 12 , further comprising causing a seventh circuit element to pull the gate of the third circuit element to ground in response to activation of the second data line.
14. The computer-implemented method of claim 12 , further comprising causing an eighth circuit element to pull the gate of the sixth circuit element to ground in response to activation of the first data line.
15. A computing device configured to perform write operations with memory cells, comprising:
a memory cell; and
a first bit line driver coupled to the memory cell and configured to write a data bit to the memory cell and including:
a first circuit element that is gated by a first write select line and coupled to a first data line configured to transport the data bit,
a second circuit element coupled to the first circuit element and gated by the first write select line, and
a third circuit element that is coupled to the memory cell and gated by the first circuit element and the second circuit element and is configured to output the data bit to the memory cell upon activation of the first data line and the first write select line.
16. The computing device of claim 15 , further comprising:
a second bit line driver coupled to the memory cell and configured to write the inverse of the data bit to the memory cell and including:
a fourth circuit element that is gated by the first write select line and coupled to a second data line configured to transport the inverse of the data bit,
a fifth circuit element coupled to the fourth circuit element and gated by the first write select line, and
a sixth circuit element coupled to the memory cell and gated by the fourth circuit element and the fifth circuit element and is configured to output the inverse of the data bit to the memory cell upon activation of the second data line and the first write select line.
17. The computing device of claim 16 , wherein the first bit line driver further includes a seventh circuit element that is coupled to the third circuit element and is gated by the second data line and is configured to pull the gate of the third circuit element to ground in response to the second write data line being activated.
18. The computing device of claim 17 , wherein the first circuit element comprises a P-channel field effect transistor, and the second circuit element, the third circuit element, and the seventh circuit element comprise N-channel field effect transistors.
19. The computing device of claim 16 , wherein the second bit line driver further includes an eighth circuit element that is coupled to the sixth circuit element and is gated by the first data line and is configured to pull the gate of the sixth circuit element to ground in response to the first write data line being activated.
20. The computing device of claim 19 , wherein the fourth circuit element comprises a P-channel field effect transistor, and the fifth circuit element, the sixth circuit element, and the eighth circuit element comprise N-channel field effect transistors.