3D UTB transistor using 2D material channels
A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.
1. A semiconductor device comprising:
a substrate;
a first dielectric layer over the substrate, the first dielectric layer having a first trench;
a two-dimensional (2D) material layer along sidewalls of the first trench;
a second dielectric layer over the 2D material layer;
a first gate electrode over the second dielectric layer; and
source and drain contacts in electrical contact with the 2D material layer on opposing sides of the first gate electrode.
2. The semiconductor device of claim 1 , wherein the first trench extends to the substrate.
3. The semiconductor device of claim 1 , wherein the 2D material layer extends along a bottom of the first trench.
4. The semiconductor device of claim 1 , wherein the 2D material layer extends over an upper surface of the first dielectric layer on opposing sides of the first trench.
5. The semiconductor device of claim 1 , wherein a portion of the first dielectric layer extends along a bottom of the first trench.
6. The semiconductor device of claim 1 , wherein the first dielectric layer has a second trench and wherein the 2D material layer extends continuously along sidewalls of the first trench and the second trench.
7. The semiconductor device of claim 1 , wherein the 2D material layer does not extend along a bottom of the first trench.
8. A semiconductor device comprising:
a substrate having a sidewall feature;
a two-dimensional (2D) material layer along sidewalls of the sidewall feature, the 2D material layer extending laterally along the sidewalls in a first direction and a second direction, the first direction being perpendicular to the second direction;
a first dielectric layer over the 2D material layer; and
a gate electrode over the first dielectric layer.
9. The semiconductor device of claim 8 , wherein the 2D material layer comprises graphene.
10. The semiconductor device of claim 8 , wherein the 2D material layer comprises a transition metal dichalcogenide (TMD).
11. The semiconductor device of claim 8 , wherein the substrate comprises an underlying substrate having a second dielectric layer thereon, wherein the sidewall feature comprises sidewalls of a trench in the second dielectric layer.
12. The semiconductor device of claim 11 , wherein the trench extends to the underlying substrate and the 2D material layer extends along sidewalls of the trench, the 2D material layer terminating at a bottom of the trench.
13. The semiconductor device of claim 11 , wherein a portion of the second dielectric layer is interposed between a bottom of the trench and the underlying substrate.
14. The semiconductor device of claim 13 , wherein the 2D material layer extends along a bottom of the trench.
15. The semiconductor device of claim 8 , wherein the substrate comprises an underlying substrate having a second dielectric layer thereon, wherein the second dielectric layer comprises a fin extending away from the underlying substrate, the 2D material layer extending along sidewalls of the fin.
16. The semiconductor device of claim 15 , wherein the second dielectric layer extends along a surface of the semiconductor substrate away from the fin, and wherein 2D material layer extends along a surface of the second dielectric layer away from the fin.
17. A method of forming a semiconductor device, the method comprising:
providing a substrate having a first dielectric layer formed thereon;
forming a fin in the first dielectric layer, the fin having sidewalls;
forming a two-dimensional (2D) material layer over the sidewalls of the fin;
forming a second dielectric layer over the 2D material layer; and
forming a gate electrode over the second dielectric layer.
18. The method of claim 17 , wherein the 2D material layer comprises graphene, a transition metal dichalcogenide (TMD), or BN.
19. The method of claim 17 , wherein the 2D material extends over an upper surface of the fin.
20. The method of claim 17 , wherein the 2D material extends over a surface of the first dielectric layer extending away from the fin.