Techniques for cache injection in a processor system using a cache injection instruction
A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.
1. A method of performing cache injection in a processor system, comprising:
monitoring, at a cache, addresses on a bus in response to a cache injection instruction, wherein the cache injection instruction causes a cache controller to modify a grab coherency bit of a coherency status field included in a cache directory to indicate that cache injection is to be employed to provide input/output data to a data block of the cache that is associated with the grab coherency bit; and
acquiring ownership of input/output data on the bus at the cache when an address on the bus, that is associated with input/output data, corresponds to an address of the data block associated with the cache injection instruction.
2. The method of claim 1 , wherein the cache injection instruction specifies the address of the data block stored in the cache.
3. The method of claim 1 , wherein the acquiring, at the cache, ownership further comprises:
storing the input/output data associated with the address on the bus in a data block of the cache at the address; and
acknowledging receipt of the input/output data.
4. The method of claim 1 , wherein the input/output data is associated with a direct memory access (DMA) write to main memory.
5. The method of claim 1 , wherein the bus includes multiple address, data, and control lines.
6. The method of claim 1 , wherein the cache injection instruction corresponds to an enhanced data cache block touch instruction.
7. The method of claim 1 , further comprising:
modifying a replacement policy position of the data block that is in the cache.
8. The method of claim 1 , wherein the cache corresponds to an L1 cache, an L2 cache, or an L3 cache.
9. A cache system, comprising:
a cache tag/data array; and
a cache controller coupled to the cache tag/data array, wherein the cache controller is configured to monitor addresses on a bus in response to a cache injection instruction that causes the cache controller to modify a grab coherency bit of a coherency status field included in a cache directory to indicate that cache injection is to be employed to provide input/output data to a data block of the cache data array that is associated with the grab coherency bit, and wherein the cache controller is configured to acquire ownership of input/output data on the bus when an address on the bus, that is associated with the input/output data, corresponds to an address of the data block associated with the cache injection instruction.
10. The cache system of claim 9 , wherein the cache injection instruction specifies the address of the data block stored in the cache data array.
11. The cache system of claim 9 , wherein the cache controller is further configured to:
store the input/output data associated with the address on the bus in a data block of the cache data array at the address; and
acknowledge receipt of the input/output data.
12. The cache system of claim 9 , wherein the input/output data is associated with a direct memory access (DMA) write to main memory.
13. The cache system of claim 9 , wherein the bus includes multiple address, data, and control lines.
14. The cache system of claim 9 , wherein the cache injection instruction corresponds to an enhanced data cache block touch instruction.
15. The cache system of claim 9 , wherein the cache controller is further configured to modify a replacement policy position of the data block that is in the cache data array.
16. The cache system of claim 9 , wherein the cache corresponds to an L1 cache, an L2 cache, or an L3 cache.
17. A processor system, comprising:
a processor; and
a cache system coupled to the processor, wherein the cache system comprises:
a cache tag/data array; and
a cache controller coupled to the cache tag/data array, wherein the cache controller is configured to monitor addresses on a bus in response to a cache injection instruction that causes the cache controller to modify a grab coherency bit of a coherency status field included in a cache directory to indicate that cache injection is to be employed to provide input/output data to a data block of the cache data array that is associated with the grab coherency bit, and wherein the cache controller is configured to acquire ownership of input/output data on the bus when an address on the bus, that is associated with the input/output data, corresponds to an address of the data block associated with the cache injection instruction.
18. The processor system of claim 17 , wherein the cache controller is further configured to:
store the input/output data associated with the address on the bus in a data block of the cache data array at the address; and
acknowledge receipt of the input/output data.
19. The processor system of claim 18 , wherein the cache injection instruction corresponds to an enhanced data cache block touch instruction.
20. The processor system of claim 19 , wherein the cache controller is further configured to modify a replacement policy position of the data block that is in the cache data array.