Memory architectures having dense layouts

1. A memory cell to store one or more bits of data, comprising:

a capacitor comprising first and second capacitor plates which are separated from one another by a dielectric, wherein the first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and wherein the second capacitor plate is a polysilicon or metal layer arranged over the doped region;

a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions, wherein a width of the gate electrode differs from a width of the second capacitor plate; and

an interconnect structure disposed over the semiconductor substrate and coupling the gate electrode of the transistor to the second capacitor plate;

wherein an upper surface of the second capacitor plate is co-planar with an upper surface of the gate electrode.

2. The memory cell of claim 1 , wherein an amount of charge to be stored in the capacitor corresponds to the one or more bits of data to be stored in the memory cell and corresponds to a resistance of a channel region between the first and second source/drain regions.

3. The memory cell of claim 1 , further comprising a memory cell wordline coupled to the first capacitor plate.

4. The memory cell of claim 3 , further comprising:

a memory cell bitline coupled to the first source/drain region; and

a memory cell sourceline coupled to the second source/drain region.

5. The memory cell of claim 1 , wherein the dielectric of the capacitor corresponds to a gate dielectric which separates the first and second capacitor plates from one another and which separates the gate electrode from the semiconductor substrate.

6. The memory cell of claim 5 , further comprising:

sidewall spacers abutting outer sidewalls of the second capacitor plate;

wherein the first capacitor plate includes: peripheral lightly doped regions which have a first conductivity type and which are arranged under the sidewall spacers, and a central lightly doped region having the first conductivity type extending continuously between the peripheral lightly doped regions.

7. The memory cell of claim 1 , further comprising:

an isolation structure arranged in the semiconductor substrate and circumscribing the capacitor or the transistor.

8. A memory array formed on a semiconductor substrate, comprising:

a plurality of memory units tiled together in rows and columns, wherein a memory unit at an intersection of a row and a column includes multiple memory cells;

a wordline extending in parallel with the row and dividing the memory cells of the memory unit into upper and lower memory cell sub-groups, wherein consecutive memory cell control gates are coupled to consecutive positions on the wordline and alternately correspond to upper and lower memory cell sub-groups;

wherein a memory cell comprises:

a capacitor comprising: a first capacitor plate, a second capacitor plate, and a dielectric separating the first and second capacitor plates, wherein the first capacitor plate is formed in the semiconductor substrate and is coupled to the wordline via a contact; and

a transistor comprising a gate electrode, a source region, and a drain region, wherein the source and drain regions are spaced apart by a channel region under the gate electrode, and wherein the gate electrode is coupled directly to the second capacitor plate and wherein a width of the gate electrode differs from a width of the second capacitor plate.

9. The memory array of claim 8 , further comprising:

first and second bitlines running perpendicular to the wordline and extending along opposite edges of the column.

10. The memory array of claim 9 , further comprising:

one or more sourcelines extending in parallel with the bitlines and arranged to divide the memory unit into left and right memory cell sub-groups.

11. The memory array of claim 8 , wherein the first capacitor plate comprises a doped conductive region in the semiconductor substrate and the second capacitor plate comprises a polysilicon or metal region aligned over the doped conductive region of the semiconductor substrate.

12. The memory array of claim 8 , wherein an amount of charge on the capacitor corresponds to a resistance of the channel region such that the resistance of the channel region is indicative of a data state stored in the memory cell.

13. A memory array formed on a semiconductor substrate, comprising:

a plurality of memory units tiled together in rows and columns, wherein a memory unit at an intersection of a row and a column includes multiple memory cells;

a wordline extending in parallel with the row and dividing the memory cells of the memory unit into an upper memory cell sub-group and a lower memory cell sub-group;

one or more sourcelines extending in parallel with the column and dividing the memory cells of the upper memory cell sub-group into an upper left sub-group and an upper right sub-group, and dividing the memory cells of the lower memory cell sub-group into a lower left sub-group and a lower right sub-group; and

a plurality of bitlines extending along outermost edges of the column;

wherein a memory cell comprises:

a capacitor comprising: a first capacitor plate, a second capacitor plate, and a dielectric separating the first and second capacitor plates, wherein the first capacitor plate is a doped region in the semiconductor substrate and is coupled to the wordline via a contact; and

a transistor comprising a gate electrode, a source region, and a drain region, wherein the source and drain regions are spaced apart by a channel region under the gate electrode, and wherein the gate electrode is coupled directly to the second capacitor plate.

14. The memory array of claim 13 :

wherein a first of the plurality of bitlines is coupled to a first memory cell arranged within the upper left sub-group;

wherein a second of the plurality of bitlines is coupled to a second memory cell arranged within the upper right sub-group;

wherein a third of the plurality of bitlines is coupled to a third memory cell arranged within the lower left sub-group; and

wherein a fourth of the plurality of bitlines is coupled to a fourth memory cell arranged within the lower right sub-group.

15. The memory array of claim 14 , wherein the first and third bitlines are arranged along a first edge of the column, and wherein the second and fourth bitlines are arranged along a second, opposite edge of the column.

16. The memory array of claim 13 , wherein consecutive memory cell control gates are coupled to consecutive positions on the wordline and alternately correspond to upper and lower memory cell sub-groups.

17. The memory array of claim 13 :

wherein a first of the one or more sourcelines is coupled to memory cells in both the upper left sub-group and the upper right sub-group without being coupled to the memory cells in the lower memory cell sub-group; and

wherein a second of the one or more sourcelines is coupled to memory cells in both the lower left sub-group and the lower right sub-group without being coupled to the memory cells in the upper memory cell sub-group.

18. The memory array of claim 13 , wherein a width of the gate electrode differs from a width of the second capacitor plate.

19. A memory cell to store one or more bits of data, comprising:

a capacitor comprising first and second capacitor plates which are separated from one another by a dielectric, wherein the first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and wherein the second capacitor plate is a polysilicon or metal layer arranged over the doped region;

a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions, wherein a width of the gate electrode differs from a width of the second capacitor plate; and

an interconnect structure disposed over the semiconductor substrate and coupling the gate electrode of the transistor to the second capacitor plate;

wherein an amount of charge to be stored in the capacitor corresponds to the one or more bits of data to be stored in the memory cell and corresponds to a resistance of a channel region between the first and second source/drain regions.

20. The memory array of claim 8 , wherein an upper surface of the second capacitor plate is co-planar with an upper surface of the gate electrode.

21. The memory array of claim 13 , wherein an upper surface of the second capacitor plate is co-planar with an upper surface of the gate electrode.